Inventor · disambiguated record
David L. O'Meara
Also filed as: O'MEARA DAVID · O'MEARA DAVID L · OMEARA DAVID L
49 granted patents·11 pending applications·1,433 citations·filing 1977–2023
98Inventor score
Top patents by PatentIndex Score
60 records- 0198US6297095B1Memory device that includes passivated nanoclusters and method for manufactureMOTOROLA INC·Filed 2000·Granted Oct 2, 2001·284 cites·17 claims
- 0297US6320784B1Memory cell and method for programming thereofMOTOROLA INC·Filed 2000·Granted Nov 20, 2001·180 cites·14 claims
- 0396US6362071B1Method for forming a semiconductor device with an opening in a dielectric layerMOTOROLA INC·Filed 2000·Granted Mar 26, 2002·149 cites·20 claims
- 0496US5972804AProcess for forming a semiconductor deviceMOTOROLA INC·Filed 1997·Granted Oct 26, 1999·181 cites·15 claims
- 0595US11195723B1Non-atomic layer deposition (ALD) method of forming sidewall passivation layer during high aspect ratio carbon layer etchTOKYO ELECTRON LTD·Filed 2020·Granted Dec 7, 2021·5 cites·20 claims
- 0695US9443731B1Material processing to achieve sub-10nm patterningTOKYO ELECTRON LTD·Filed 2015·Granted Sep 13, 2016·21 cites·20 claims
- 0794US6344403B1Memory device and method for manufactureMOTOROLA INC·Filed 2000·Granted Feb 5, 2002·142 cites·7 claims
- 0894US4981724ADeposition of silicon oxide films using alkylsilane liquid sourcesHOCHBERG ARTHUR K·Filed 1977·Granted Jan 1, 1991·84 cites·10 claims
- 0993US9171736B2Spacer material modification to improve K-value and etch propertiesTOKYO ELECTRON LTD·Filed 2014·Granted Oct 27, 2015·16 cites·17 claims
- 1092US9831099B2Method and apparatus for multi-film deposition and etching in a batch processing systemTOKYO ELECTRON LTD·Filed 2017·Granted Nov 28, 2017·8 cites·19 claims
- 1192US4992306ADeposition of silicon dioxide and silicon oxynitride films using azidosilane sourcesAIR PRODUCTS ABD CHEMICALS INC·Filed 1990·Granted Feb 12, 1991·127 cites·25 claims
- 1290US10770294B2Selective atomic layer deposition (ALD) of protective caps to enhance extreme ultra-violet (EUV) etch resistanceTOKYO ELECTRON LTD·Filed 2019·Granted Sep 8, 2020·6 cites·21 claims
- 1390US8673725B2Multilayer sidewall spacer for seam protection of a patterned structureO'MEARA DAVID L·Filed 2010·Granted Mar 18, 2014·15 cites·12 claims
- 1488US11024535B2Method for filling recessed features in semiconductor devices with a low-resistivity metalTOKYO ELECTRON LTD·Filed 2019·Granted Jun 1, 2021·4 cites·19 claims
- 1585US6297173B1Process for forming a semiconductor deviceMOTOROLA INC·Filed 1999·Granted Oct 2, 2001·52 cites·21 claims
- 1683US9899224B2Method of controlling solid phase diffusion of boron dopants to form ultra-shallow doping regionsTOKYO ELECTRON LTD·Filed 2016·Granted Feb 20, 2018·4 cites·20 claims
- 1782US8809169B2Multi-layer pattern for alternate ALD processesO'MEARA DAVID L·Filed 2011·Granted Aug 19, 2014·6 cites·19 claims
- 1878US7509962B2Method and control system for treating a hafnium-based dielectric processing systemTOKYO ELECTRON LTD·Filed 2005·Granted Mar 31, 2009·7 cites·26 claims
- 1978US6974779B2Interfacial oxidation process for high-k gate dielectric process integrationIBM·Filed 2003·Granted Dec 13, 2005·20 cites·33 claims
- 2077US11164781B2ALD (atomic layer deposition) liner for via profile control and related applicationsTOKYO ELECTRON LTD·Filed 2019·Granted Nov 2, 2021·2 cites·20 claims
- 2172US2024047218A1Systems and methods for improving planarity using selective atomic layer etching (ale)TOKYO ELECTRON LTD·Filed 2023·Application pending·0 cites
- 2270US10580650B2Method for bottom-up formation of a film in a recessed featureTOKYO ELECTRON LTD·Filed 2017·Granted Mar 3, 2020·1 cites·20 claims
- 2370US7470591B2Method of forming a gate stack containing a gate dielectric layer having reduced metal contentTOKYO ELECTRON LTD·Filed 2005·Granted Dec 30, 2008·4 cites·23 claims
- 2470US6686633B1Semiconductor device, memory cell, and processes for forming themMOTOROLA INC·Filed 2000·Granted Feb 3, 2004·16 cites·20 claims
- 2569US4992299ADeposition of silicon nitride films from azidosilane sourcesAIR PROD & CHEM·Filed 1990·Granted Feb 12, 1991·44 cites·24 claims
- 2668US11651967B2Non-atomic layer deposition (ALD) method of forming sidewall passivation layer during high aspect ratio carbon layer etchTOKYO ELECTRON LTD·Filed 2021·Granted May 16, 2023·0 cites·20 claims
- 2765US11742241B2ALD (atomic layer deposition) liner for via profile control and related applicationsTOKYO ELECTRON LTD·Filed 2021·Granted Aug 29, 2023·0 cites·19 claims
- 2865US7501352B2Method and system for forming an oxynitride layerTOKYO ELECTRON LTD·Filed 2005·Granted Mar 10, 2009·3 cites·163 claims
- 2964US11621190B2Method for filling recessed features in semiconductor devices with a low-resistivity metalTOKYO ELECTRON LTD·Filed 2021·Granted Apr 4, 2023·0 cites·20 claims
- 3064US6184073B1Process for forming a semiconductor device having an interconnect or conductive film electrically insulated from a conductive member or regionMOTOROLA INC·Filed 1997·Granted Feb 6, 2001·27 cites·14 claims
- 3160US11823910B2Systems and methods for improving planarity using selective atomic layer etching (ALE)TOKYO ELECTRON LTD·Filed 2020·Granted Nov 21, 2023·0 cites·18 claims
- 3258US8664102B2Dual sidewall spacer for seam protection of a patterned structureO'MEARA DAVID L·Filed 2010·Granted Mar 4, 2014·1 cites·13 claims
- 3355US12451354B2Double patterning method of patterning a substrateTOKYO ELECTRON LTD·Filed 2022·Granted Oct 21, 2025·0 cites·16 claims
- 3455US8785310B2Method of forming conformal metal silicide filmsHASEGAWA TOSHIO·Filed 2012·Granted Jul 22, 2014·1 cites·22 claims
- 3555US2025087628A1Method of surface modification for wafer bondingTOKYO ELECTRON LTD·Filed 2023·Application pending·0 cites
- 3655US2024153770A1Method of Profile Control for Semiconductor ManufacturingTOKYO ELECTRON LTD·Filed 2022·Application pending·0 cites
- 3754US7235440B2Formation of ultra-thin oxide layers by self-limiting interfacial oxidationIBM·Filed 2003·Granted Jun 26, 2007·5 cites·12 claims
- 3854US2024420965A1Method of deposition in high aspect ratio (har) featuresTOKYO ELECTRON LTD·Filed 2023·Application pending·0 cites
- 3953US12400872B2Sacrificial capping layer for gate protectionTOKYO ELECTRON LTD·Filed 2022·Granted Aug 26, 2025·0 cites·20 claims
- 4053US10978307B2Deposition processTOKYO ELECTRON LTD·Filed 2020·Granted Apr 13, 2021·0 cites·20 claims
- 4152US8460945B2Method for monitoring status of system componentsO'MEARA DAVID L·Filed 2003·Granted Jun 11, 2013·2 cites·4 claims
- 4251US11567407B2Method for globally adjusting spacer critical dimension using photo-active self-assembled monolayerTOKYO ELECTRON LTD·Filed 2019·Granted Jan 31, 2023·0 cites·18 claims
- 4351US10734228B2Manufacturing methods to apply stress engineering to self-aligned multi-patterning (SAMP) processesTOKYO ELECTRON LTD·Filed 2018·Granted Aug 4, 2020·0 cites·20 claims
- 4450US10700009B2Ruthenium metal feature fill for interconnectsTOKYO ELECTRON LTD·Filed 2018·Granted Jun 30, 2020·0 cites·20 claims
- 4549US11621164B2Method for critical dimension (CD) trim of an organic pattern used for multi-patterning purposesTOKYO ELECTRON LTD·Filed 2020·Granted Apr 4, 2023·0 cites·20 claims
- 4649US11532517B2Localized etch stop layerTOKYO ELECTRON LTD·Filed 2020·Granted Dec 20, 2022·0 cites·16 claims
- 4749US10079151B2Method for bottom-up deposition of a film in a recessed featureTOKYO ELECTRON LTD·Filed 2016·Granted Sep 18, 2018·0 cites·16 claims
- 4849US2022139776A1Method for filling recessed features in semiconductor devices with a low-resistivity metalTOKYO ELECTRON LTD·Filed 2021·Application pending·0 cites
- 4947US11417526B2Multiple patterning processesTOKYO ELECTRON LTD·Filed 2020·Granted Aug 16, 2022·0 cites·20 claims
- 5046US7479454B2Method and processing system for monitoring status of system componentsTOKYO ELECTRON LTD·Filed 2003·Granted Jan 20, 2009·3 cites·20 claims
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