Inventor · disambiguated record
Clinton Chao
Also filed as: CHAO CLINTON · CHAO CLINTON C · CHAO CLINTON CHIH-CHIEH
42 granted patents·6 pending applications·1,361 citations·filing 1987–2021
98Inventor score
Files withTAIWAN SEMICONDUCTOR MFG21HEWLETT PACKARD CO8TAIWAN SEMICONDUCTOR MFG CO LTD5LEE CHIEN HSIUN3LU SZU WEI2
Top patents by PatentIndex Score
48 records- 0199US7576435B2Low-cost and ultra-fine integrated circuit packaging techniqueTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Aug 18, 2009·255 cites·20 claims
- 0297US7427803B2Electromagnetic shielding using through-silicon viasTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Sep 23, 2008·84 cites·18 claims
- 0394US7494846B2Design techniques for stacking identical memory diesTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Feb 24, 2009·42 cites·16 claims
- 0493US8945998B2Programmable semiconductor interposer for electronic package and method of formingTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Feb 3, 2015·15 cites·21 claims
- 0593US7804177B2Silicon-based thin substrate and packaging schemesTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Sep 28, 2010·31 cites·11 claims
- 0693US5055425AStacked solid via formation in integrated circuit systemsHEWLETT PACKARD CO·Filed 1989·Granted Oct 8, 1991·121 cites·8 claims
- 0792US7112522B1Method to increase bump height and achieve robust bump structureTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Sep 26, 2006·25 cites·15 claims
- 0891US7795735B2Methods for forming single dies with multi-layer interconnect structures and structures formed therefromTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Sep 14, 2010·30 cites·17 claims
- 0991US7514775B2Stacked structures and methods of fabricating stacked structuresTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Apr 7, 2009·24 cites·21 claims
- 1090US11935842B2Methods of manufacturing an integrated circuit having stress tuning layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Mar 19, 2024·1 cites·20 claims
- 1190US5029386AHierarchical tape automated bonding methodHEWLETT PACKARD CO·Filed 1990·Granted Jul 9, 1991·206 cites·13 claims
- 1289US8476735B2Programmable semiconductor interposer for electronic package and method of formingHSU CHAO-SHUN·Filed 2007·Granted Jul 2, 2013·26 cites·20 claims
- 1389US8426256B2Method of forming stacked-die packagesHSIAO C W·Filed 2010·Granted Apr 23, 2013·21 cites·20 claims
- 1489US5162260AStacked solid via formation in integrated circuit systemsHEWLETT PACKARD CO·Filed 1991·Granted Nov 10, 1992·124 cites·6 claims
- 1588US8367474B2Method of manufacturing integrated circuit having stress tuning layerTAIWAN SEMICONDUCTOR MFG·Filed 2011·Granted Feb 5, 2013·6 cites·20 claims
- 1688US7880278B2Integrated circuit having stress tuning layerTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Feb 1, 2011·10 cites·16 claims
- 1788US7750651B2Wafer level test probe cardTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Jul 6, 2010·18 cites·10 claims
- 1887US5633535ASpacing control in electronic device assembliesFiled 1995·Granted May 27, 1997·156 cites·9 claims
- 1986US11094646B2Methods of manufacturing an integrated circuit having stress tuning layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Aug 17, 2021·2 cites·20 claims
- 2086US7812426B2TSV-enabled twisted pairTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Oct 12, 2010·14 cites·18 claims
- 2183US10269730B2Methods of manufacturing an integrated circuit having stress tuning layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Apr 23, 2019·2 cites·20 claims
- 2283US9633954B2Methods of manufacturing an integrated circuit having stress tuning layerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Apr 25, 2017·2 cites·20 claims
- 2382US8334170B2Method for stacking devicesWANG DEAN·Filed 2008·Granted Dec 18, 2012·10 cites·14 claims
- 2479US8322020B2Method for fabricating a semiconductor test probe card space transformerHSU MING CHENG·Filed 2011·Granted Dec 4, 2012·5 cites·18 claims
- 2575US7565635B2SiP (system in package) design systems and methodsTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Jul 21, 2009·9 cites·18 claims
- 2674US8146245B2Method for assembling a wafer level test probe cardCHAO CLINTON CHIH-CHIEH·Filed 2010·Granted Apr 3, 2012·4 cites·20 claims
- 2773US8033012B2Method for fabricating a semiconductor test probe card space transformerTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Oct 11, 2011·5 cites·11 claims
- 2868US8174129B2Silicon-based thin substrate and packaging schemesLU SZU WEI·Filed 2010·Granted May 8, 2012·2 cites·20 claims
- 2962US8551813B2Wafer level IC assembly methodLEE CHIEN HSIUN·Filed 2012·Granted Oct 8, 2013·1 cites·20 claims
- 3062US5221421AControlled etching process for forming fine-geometry circuit lines on a substrateHEWLETT PACKARD CO·Filed 1992·Granted Jun 22, 1993·35 cites·26 claims
- 3161US8704383B2Silicon-based thin substrate and packaging schemesLU SZU-WEI·Filed 2012·Granted Apr 22, 2014·1 cites·22 claims
- 3258US9275948B2Integrated circuit having stress tuning layerTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted Mar 1, 2016·0 cites·20 claims
- 3357US7977155B2Wafer-level flip-chip assembly methodsTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Jul 12, 2011·1 cites·5 claims
- 3454US7642793B2Ultra-fine pitch probe card structureTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Jan 5, 2010·2 cites·20 claims
- 3553US7696766B2Ultra-fine pitch probe card structureTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Apr 13, 2010·2 cites·28 claims
- 3652US2009174071A1Semiconductor device including electrically conductive bump and method of manufacturing the sameTAIWAN SEMICONDUCTOR MFG·Filed 2009·Application pending·0 cites
- 3751US8247267B2Wafer level IC assembly methodLEE CHIEN HSIUN·Filed 2008·Granted Aug 21, 2012·0 cites·10 claims
- 3850US6242075B1Planar multilayer ceramic structures with near surface channelsHEWLETT PACKARD CO·Filed 1998·Granted Jun 5, 2001·19 cites·20 claims
- 3950US4782381AChip carrierHEWLETT PACKARD CO·Filed 1987·Granted Nov 1, 1988·16 cites·2 claims
- 4049US2010174858A1Extra high bandwidth memory die stackTAIWAN SEMICONDUCTOR MFG·Filed 2009·Application pending·0 cites
- 4149US2013127049A1Method for Stacking Devices and Structure ThereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2012·Application pending·0 cites
- 4247US2007267745A1Semiconductor device including electrically conductive bump and method of manufacturing the sameTAIWAN SEMICONDUCTOR MFG·Filed 2006·Application pending·0 cites
- 4345US5200300AMethods for forming high density multi-chip carriersHEWLETT PACKARD CO·Filed 1991·Granted Apr 6, 1993·16 cites·15 claims
- 4443US8232183B2Process and apparatus for wafer-level flip-chip assemblyLEE CHIEN-HSIUN·Filed 2007·Granted Jul 31, 2012·0 cites·14 claims
- 4541US5399528AMulti-layer fabrication in integrated circuit systemsFiled 1993·Granted Mar 21, 1995·9 cites·5 claims
- 4641US2007246821A1Utra-thin substrate package technologyLU SZU W·Filed 2006·Application pending·0 cites
- 4738US5086335ATape automated bonding system which facilitate repairHEWLETT PACKARD CO·Filed 1990·Granted Feb 4, 1992·9 cites·2 claims
- 4837US2008018350A1Test probe for integrated circuits with ultra-fine pitch terminalsCHAO CLINTON·Filed 2006·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →