Inventor · disambiguated record
Jasmeet S. Chawla
Also filed as: CHAWLA JASMEET · CHAWLA JASMEET S
20 granted patents·3 pending applications·115 citations·filing 2013–2025
94Inventor score
Top patents by PatentIndex Score
23 records- 0197US9054164B1Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenchesJEZEWSKI CHRISTOPHER J·Filed 2013·Granted Jun 9, 2015·41 cites·25 claims
- 0293US10032643B2Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and encapsulating etchstop liner schemeINTEL CORP·Filed 2014·Granted Jul 24, 2018·16 cites·25 claims
- 0393US9385082B2Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenchesINTEL CORP·Filed 2015·Granted Jul 5, 2016·7 cites·19 claims
- 0489US9548269B2Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnectsMYERS ALAN M·Filed 2015·Granted Jan 17, 2017·7 cites·9 claims
- 0589US9209077B2Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnectsMYERS ALAN M·Filed 2013·Granted Dec 8, 2015·10 cites·17 claims
- 0688US11107908B2Transistors with metal source and drain contacts including a Heusler alloyINTEL CORP·Filed 2016·Granted Aug 31, 2021·5 cites·21 claims
- 0788US2025357335A1Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenchesTAHOE RES LTD·Filed 2025·Application pending·0 cites
- 0887US10957844B2Magneto-electric spin orbit (MESO) structures having functional oxide viasINTEL CORP·Filed 2016·Granted Mar 23, 2021·3 cites·23 claims
- 0986US10497613B2Microelectronic conductive routes and methods of making the sameINTEL CORP·Filed 2015·Granted Dec 3, 2019·5 cites·14 claims
- 1085US12394716B2Integrated circuit interconnect structures with graphene capINTEL CORP·Filed 2021·Granted Aug 19, 2025·1 cites·19 claims
- 1184US11056593B2Semiconductor devices with metal contacts including crystalline alloysINTEL CORP·Filed 2017·Granted Jul 6, 2021·3 cites·19 claims
- 1283US11380617B2Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenchesINTEL CORP·Filed 2018·Granted Jul 5, 2022·2 cites·20 claims
- 1382US10256141B2Maskless air gap to prevent via punch throughINTEL CORP·Filed 2015·Granted Apr 9, 2019·3 cites·20 claims
- 1481US9911694B2Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenchesINTEL CORP·Filed 2016·Granted Mar 6, 2018·2 cites·20 claims
- 1579US12322699B2Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenchesTAHOE RES LTD·Filed 2022·Granted Jun 3, 2025·0 cites·20 claims
- 1679US10109583B2Method for creating alternate hardmask cap interconnect structure with increased overlay marginINTEL CORP·Filed 2014·Granted Oct 23, 2018·4 cites·25 claims
- 1777US9379010B2Methods for forming interconnect layers having tight pitch interconnect structuresINTEL CORP·Filed 2014·Granted Jun 28, 2016·4 cites·22 claims
- 1869US11069609B2Techniques for forming vias and other interconnects for integrated circuit structuresINTEL CORP·Filed 2017·Granted Jul 20, 2021·1 cites·20 claims
- 1968US10546772B2Self-aligned via below subtractively patterned interconnectINTEL CORP·Filed 2016·Granted Jan 28, 2020·1 cites·20 claims
- 2058US10971394B2Maskless air gap to prevent via punch throughINTEL CORP·Filed 2019·Granted Apr 6, 2021·0 cites·15 claims
- 2152US2024421101A1Backside contact based die edge guard ringsINTEL CORP·Filed 2023·Application pending·0 cites
- 2244US10707186B1Compliant layer for wafer to wafer bondingINTEL CORP·Filed 2018·Granted Jul 7, 2020·0 cites·8 claims
- 2336US2019074217A1Conductive connectors having a ruthenium/aluminum-containing liner and methods of fabricating the sameINTEL CORP·Filed 2016·Application pending·0 cites
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