Inventor · disambiguated record
Basab Bandyopadhyay
Also filed as: BANDYOPADHYAY BASAB
56 granted patents·2,172 citations·filing 1995–2002
99Inventor score
Top patents by PatentIndex Score
56 records- 0198US5850105ASubstantially planar semiconductor topography using dielectrics and chemical mechanical polishADVANCED MICRO DEVICES INC·Filed 1997·Granted Dec 15, 1998·278 cites·10 claims
- 0294US5953626ADissolvable dielectric methodADVANCED MICRO DEVICES INC·Filed 1996·Granted Sep 14, 1999·160 cites·12 claims
- 0393US5759913AMethod of formation of an air gap within a semiconductor dielectric by solvent desorptionADVANCED MICRO DEVICES INC·Filed 1996·Granted Jun 2, 1998·148 cites·17 claims
- 0492US5827776AMethod of making an integrated circuit which uses an etch stop for producing staggered interconnect linesADVANCED MICRO DEVICES INC·Filed 1997·Granted Oct 27, 1998·139 cites·14 claims
- 0590US6037671AStepper alignment mark structure for maintaining alignment integrityADVANCED MICRO DEVICES INC·Filed 1998·Granted Mar 14, 2000·107 cites·21 claims
- 0688US5792706AInterlevel dielectric with air gaps to reduce permitivityADVANCED MICRO DEVICES INC·Filed 1996·Granted Aug 11, 1998·96 cites·20 claims
- 0787US5783864AMultilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnectADVANCED MICRO DEVICES INC·Filed 1996·Granted Jul 21, 1998·78 cites·5 claims
- 0885US5930645AShallow trench isolation formation with reduced polish stop thicknessADVANCED MICRO DEVICES INC·Filed 1997·Granted Jul 27, 1999·87 cites·17 claims
- 0984US5814555AInterlevel dielectric with air gaps to lessen capacitive couplingADVANCED MICRO DEVICES INC·Filed 1996·Granted Sep 29, 1998·63 cites·11 claims
- 1083US5926713AMethod for achieving global planarization by forming minimum mesas in large field areasADVANCED MICRO DEVICES INC·Filed 1997·Granted Jul 20, 1999·69 cites·26 claims
- 1182US6171962B1Shallow trench isolation formation without planarization maskADVANCED MICRO DEVICES INC·Filed 1997·Granted Jan 9, 2001·68 cites·11 claims
- 1281US6208015B1Interlevel dielectric with air gaps to lessen capacitive couplingADVANCED MICRO DEVICES INC·Filed 1998·Granted Mar 27, 2001·51 cites·21 claims
- 1381US5899727AMethod of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarizationADVANCED MICRO DEVICES INC·Filed 1996·Granted May 4, 1999·56 cites·18 claims
- 1481US5811334AWafer cleaning procedure useful in the manufacture of a non-volatile memory deviceADVANCED MICRO DEVICES INC·Filed 1995·Granted Sep 22, 1998·53 cites·11 claims
- 1578US5998293AMultilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnectADVANCED MICRO DEVCIES INC·Filed 1998·Granted Dec 7, 1999·54 cites·11 claims
- 1676US6376330B1Dielectric having an air gap formed between closely spaced interconnect linesADVANCED MICRO DEVICES INC·Filed 1996·Granted Apr 23, 2002·48 cites·13 claims
- 1773US6091149ADissolvable dielectric method and structureADVANCED MICRO DEVICES INC·Filed 1999·Granted Jul 18, 2000·37 cites·6 claims
- 1872US5926717AMethod of making an integrated circuit with oxidizable trench linerADVANCED MICRO DEVICES INC·Filed 1996·Granted Jul 20, 1999·41 cites·25 claims
- 1971US6143624AShallow trench isolation formation with spacer-assisted ion implantationADVANCED MICRO DEVICES INC·Filed 1998·Granted Nov 7, 2000·42 cites·24 claims
- 2071US5846876AIntegrated circuit which uses a damascene process for producing staggered interconnect linesADVANCED MICRO DEVICES INC·Filed 1996·Granted Dec 8, 1998·35 cites·9 claims
- 2168US6074927AShallow trench isolation formation with trench wall spacerADVANCED MICRO DEVICES INC·Filed 1998·Granted Jun 13, 2000·37 cites·17 claims
- 2264US6599810B1Shallow trench isolation formation with ion implantationADVANCED MICRO DEVICES INC·Filed 1998·Granted Jul 29, 2003·29 cites·21 claims
- 2364US5783481ASemiconductor interlevel dielectric having a polymide for producing air gapsADVANCED MICRO DEVICES INC·Filed 1996·Granted Jul 21, 1998·29 cites·17 claims
- 2461US5767012AMethod of forming a recessed interconnect structureADVANCED MICRO DEVICES INC·Filed 1996·Granted Jun 16, 1998·22 cites·10 claims
- 2561US5717242AIntegrated circuit having local interconnect for reduing signal cross coupled noiseADVANCED MICRO DEVICES INC·Filed 1996·Granted Feb 10, 1998·22 cites·20 claims
- 2659US6380047B1Shallow trench isolation formation with two source/drain masks and simplified planarization maskADVANCED MICRO DEVICES INC·Filed 2000·Granted Apr 30, 2002·9 cites·17 claims
- 2759US6124183AShallow trench isolation formation with simplified reverse planarization maskADVANCED MICRO DEVICES INC·Filed 1997·Granted Sep 26, 2000·25 cites·13 claims
- 2858US5968843AMethod of planarizing a semiconductor topography using multiple polish padsADVANCED MICRO DEVICES INC·Filed 1996·Granted Oct 19, 1999·21 cites·7 claims
- 2957US6165906ASemiconductor topography employing a shallow trench isolation structure with an improved trench edgeADVANCED MICRO DEVICES INC·Filed 1999·Granted Dec 26, 2000·22 cites·20 claims
- 3057US6130467AShallow trench isolation with spacers for improved gate oxide qualityADVANCED MICRO DEVICES INC·Filed 1997·Granted Oct 10, 2000·23 cites·2 claims
- 3155US6720227B1Method of forming source/drain regions in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2002·Granted Apr 13, 2004·4 cites·34 claims
- 3255US5924008AIntegrated circuit having local interconnect for reducing signal cross coupled noiseADVANCED MICRO DEVICES INC·Filed 1997·Granted Jul 13, 1999·17 cites·4 claims
- 3353US5970363AShallow trench isolation formation with improved trench edge oxideADVANCED MICRO DEVICES INC·Filed 1997·Granted Oct 19, 1999·19 cites·30 claims
- 3452US6150721AIntegrated circuit which uses a damascene process for producing staggered interconnect linesADVANCED MICRO DEVICES INC·Filed 1998·Granted Nov 21, 2000·15 cites·21 claims
- 3551US5970362ASimplified shallow trench isolation formation with no polish stopADVANCED MICRO DEVICES INC·Filed 1997·Granted Oct 19, 1999·17 cites·14 claims
- 3651US5854131AIntegrated circuit having horizontally and vertically offset interconnect linesADVANCED MICRO DEVICES INC·Filed 1996·Granted Dec 29, 1998·14 cites·10 claims
- 3750US5733798AMask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarizationADVANCED MICRO DEVICES INC·Filed 1996·Granted Mar 31, 1998·13 cites·13 claims
- 3848US6326298B1Substantially planar semiconductor topography using dielectrics and chemical mechanical polishADVANCED MICRO DEVICES INC·Filed 2000·Granted Dec 4, 2001·2 cites·9 claims
- 3947US5830773AMethod for forming semiconductor field region dielectrics having globally planarized upper surfacesADVANCED MICRO DEVICES INC·Filed 1996·Granted Nov 3, 1998·13 cites·16 claims
- 4046US6031289AIntegrated circuit which uses a recessed local conductor for producing staggered interconnect linesADVANCED MICRO DEVICES INC·Filed 1998·Granted Feb 29, 2000·11 cites·12 claims
- 4146US5851913AMethod for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill processADVANCED MICRO DEVICES INC·Filed 1996·Granted Dec 22, 1998·13 cites·20 claims
- 4245US6153833AIntegrated circuit having interconnect lines separated by a dielectric having a capping layerADVANCED MICRO DEVICES INC·Filed 1998·Granted Nov 28, 2000·10 cites·20 claims
- 4345US6127264AIntegrated circuit having conductors of enhanced cross-sectional areaADVANCED MICRO DEVICES INC·Filed 1998·Granted Oct 3, 2000·10 cites·8 claims
- 4445US6090703AMethod of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layerADVANCED MICRO DEVICES INC·Filed 1998·Granted Jul 18, 2000·10 cites·10 claims
- 4544US5766803AMask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarizationADVANCED MICRO DEVICES INC·Filed 1996·Granted Jun 16, 1998·9 cites·6 claims
- 4642US5847462AIntegrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layerADVANCED MICRO DEVICES INC·Filed 1996·Granted Dec 8, 1998·8 cites·15 claims
- 4739US6309947B1Method of manufacturing a semiconductor device with improved isolation region to active region topographyADVANCED MICRO DEVICES INC·Filed 1997·Granted Oct 30, 2001·7 cites·19 claims
- 4839US5854515AIntegrated circuit having conductors of enhanced cross-sectional areaADVANCED MICRO DEVICES INC·Filed 1996·Granted Dec 29, 1998·6 cites·12 claims
- 4938US5894168AMask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarizationADVANCED MICRO DEVICES INC·Filed 1997·Granted Apr 13, 1999·5 cites·5 claims
- 5037US5767000AMethod of manufacturing subfield conductive layerADVANCED MICRO DEVICES INC·Filed 1996·Granted Jun 16, 1998·5 cites·10 claims
Showing the top 50 of 56 patent records by PatentIndex Score.
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