Inventor · disambiguated record
Yusuke Matsunaga
Also filed as: MATSUNAGA YUSUKE
14 granted patents·158 citations·filing 1991–2017
92Inventor score
Top patents by PatentIndex Score
14 records- 0190US9810738B2Semiconductor device, diagnostic test, and diagnostic test circuitRENESAS ELECTRONICS CORP·Filed 2015·Granted Nov 7, 2017·7 cites·20 claims
- 0276US7059050B2One piece integral reinforcement with angled end caps to facilitate assembly to coreDELPHI TECH INC·Filed 2004·Granted Jun 13, 2006·19 cites·6 claims
- 0372US7490271B2Semiconductor device mounting chip having tracing functionRENESAS TECH CORP·Filed 2006·Granted Feb 10, 2009·5 cites·10 claims
- 0464US7260893B2Method of attaching a transmission oil cooler to an aluminum tankDELPHI TECH INC·Filed 2004·Granted Aug 28, 2007·9 cites·8 claims
- 0562US5490268AMethod for changing an arrangement of an initial combinational circuit to satisfy prescribed delay time by computing permissible functions of output gates and remaining gatesFUJITSU LTD·Filed 1991·Granted Feb 6, 1996·35 cites·4 claims
- 0661US10520549B2Semiconductor device, diagnostic test, and diagnostic test circuitRENESAS ELECTRONICS CORP·Filed 2017·Granted Dec 31, 2019·0 cites·15 claims
- 0758US5461574AMethod of expressing a logic circuitFUJITSU LTD·Filed 1995·Granted Oct 24, 1995·35 cites·8 claims
- 0855US7146543B2Semiconductor device mounting chip having tracing functionRENESAS TECH CORP·Filed 2003·Granted Dec 5, 2006·6 cites·5 claims
- 0954US7007743B2Header tank with integral mounting flangeDELPHI TECH INC·Filed 2003·Granted Mar 7, 2006·6 cites·18 claims
- 1046US7147040B2Heat exchanger with tank utilizing integral positioning guidesDELPHI TECH INC·Filed 2004·Granted Dec 12, 2006·2 cites·9 claims
- 1142US5909374ASystem and method for verifying logic circuit based on signal line set affecting internal signalFUJITSU LTD·Filed 1996·Granted Jun 1, 1999·16 cites·14 claims
- 1241US6625799B2Technology mapping method and storage mediumFUJITSU LTD·Filed 2000·Granted Sep 23, 2003·0 cites·12 claims
- 1341US5535132AVariable sequence determining method for a dichotomy determination graphFUJITSU LTD·Filed 1992·Granted Jul 9, 1996·13 cites·8 claims
- 1433US5734917ASystem for producing combination circuit to satisfy prescribed delay time by deleting selected path gate and allowing to perform the permissible function for initial circuitFUJITSU LTD·Filed 1995·Granted Mar 31, 1998·5 cites·4 claims
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