Inventor · disambiguated record
Sergio Schuler
Also filed as: SCHULER SERGIO
14 granted patents·3 pending applications·59 citations·filing 2006–2024
90Inventor score
Files withMYTHIC INC10ADVANCED RISC MACH LTD3FREESCALE SEMICONDUCTOR INC2BRUCE KLAS M1SCHULER SERGIO1
Top patents by PatentIndex Score
17 records- 0197US11049586B2Systems and methods for implementing redundancy for tile-based intelligence processing computing architectureMYTHIC INC·Filed 2020·Granted Jun 29, 2021·8 cites·16 claims
- 0296US11016810B1Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2020·Granted May 25, 2021·15 cites·15 claims
- 0394US11360932B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2020·Granted Jun 14, 2022·5 cites·18 claims
- 0491US10521395B1Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2019·Granted Dec 31, 2019·6 cites·16 claims
- 0588US12013807B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2022·Granted Jun 18, 2024·1 cites·18 claims
- 0686US10606797B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2019·Granted Mar 31, 2020·3 cites·12 claims
- 0786US7681021B2Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branchFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Mar 16, 2010·19 cites·10 claims
- 0881US12461888B2Systems and methods for implementing an intelligence processing computing architectureMYTHIC INC·Filed 2024·Granted Nov 4, 2025·0 cites·16 claims
- 0978US2024311194A1Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2024·Application pending·0 cites
- 1069US12014214B2Tile subsystem and method for automated data flow and data processing within an integrated circuit architectureMYTHIC INC·Filed 2021·Granted Jun 18, 2024·0 cites·19 claims
- 1166US11475973B2Systems and methods for implementing redundancy for tile-based intelligence processing computing architectureMYTHIC INC·Filed 2021·Granted Oct 18, 2022·0 cites·20 claims
- 1263US11915005B1Branch predictor triggeringADVANCED RISC MACH LTD·Filed 2022·Granted Feb 27, 2024·0 cites·17 claims
- 1357US2025390309A1Technique for generating predictions of a target address of branch instructionsADVANCED RISC MACH LTD·Filed 2024·Application pending·0 cites
- 1456US8832702B2Thread de-emphasis instruction for multithreaded processorBRUCE KLAS M·Filed 2007·Granted Sep 9, 2014·2 cites·20 claims
- 1546US10891084B2Apparatus and method for providing data to a master deviceADVANCED RISC MACH LTD·Filed 2019·Granted Jan 12, 2021·0 cites·17 claims
- 1646US7805581B2Multiple address and arithmetic bit-mode data processing device and methods thereofFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Sep 28, 2010·0 cites·20 claims
- 1744US2009249048A1Branch target buffer addressing in a data processorSCHULER SERGIO·Filed 2008·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →