Inventor · disambiguated record
Donald Oriordan
Also filed as: ORIORDAN DONALD · Oriordan Donald John
15 granted patents·31 pending applications·51 citations·filing 2017–2025
90Inventor score
Top patents by PatentIndex Score
46 records- 0191US2025371241A1Computing parasitic values for semiconductor designsD2S INC·Filed 2025·Application pending·0 cites
- 0290US11790127B1Full correlation aging analysis over combined process voltage temperature variationSYNOPSYS INC·Filed 2020·Granted Oct 17, 2023·3 cites·20 claims
- 0390US10102324B2Reuse of extracted layout-dependent effects for circuit design using circuit stencilsSYNOPSYS INC·Filed 2017·Granted Oct 16, 2018·7 cites·21 claims
- 0489US10719650B1Hierarchical dynamic heat maps in full custom EDA applicationsSYNOPSYS INC·Filed 2018·Granted Jul 21, 2020·19 cites·21 claims
- 0589US10078715B2Integrated circuit design using generation and instantiation of circuit stencilsSYNOPSYS INC·Filed 2017·Granted Sep 18, 2018·7 cites·23 claims
- 0688US10896274B1Extreme cases sampling method for improved variation-aware full custom designSYNOPSYS INC·Filed 2019·Granted Jan 19, 2021·9 cites·27 claims
- 0785US2025068058A1Iterative mask optimization biased towards critical regions of layoutD2S INC·Filed 2024·Application pending·0 cites
- 0885US2025068052A1Mask optimization for layer based on comparison of components in layer to components in other layersD2S INC·Filed 2024·Application pending·0 cites
- 0985US2025068051A1Mask optimization for first layer that accounts for other layersD2S INC·Filed 2024·Application pending·0 cites
- 1085US2025068053A1Mask optimization accounting for more critical and less critical overlap regionsD2S INC·Filed 2024·Application pending·0 cites
- 1185US2025068056A1Mask optimization for layer accounting for overlap with other layersD2S INC·Filed 2024·Application pending·0 cites
- 1285US2025102899A1Mask optimization preferentially accounting for overlap regionsD2S INC·Filed 2024·Application pending·0 cites
- 1385US2025068057A1Concurrent mask optimization for multiple layersD2S INC·Filed 2024·Application pending·0 cites
- 1484US2025068825A1Parasitics extraction based on multiple manufacturing process variationsD2S INC·Filed 2024·Application pending·0 cites
- 1584US2025068810A1Generation of 3-d shapes for eda operationsD2S INC·Filed 2024·Application pending·0 cites
- 1684US2025068826A1Variation in taper angles of predicted manufactured shapes for parasitics extractionD2S INC·Filed 2024·Application pending·0 cites
- 1784US2025068809A1Generation of 3-d shapes for eda operationsD2S INC·Filed 2024·Application pending·0 cites
- 1884US2025068824A1High accuracy parasitics extractionD2S INC·Filed 2024·Application pending·0 cites
- 1983US2025068808A1Generation of 3-d shapes for eda operationsD2S INC·Filed 2024·Application pending·0 cites
- 2080US12372864B2Methods and systems to determine shapes for semiconductor or flat panel display fabricationD2S INC·Filed 2020·Granted Jul 29, 2025·1 cites·26 claims
- 2180US10521535B2Reuse of extracted layout-dependent effects for circuit design using circuit stencilsSYNOPSYS INC·Filed 2017·Granted Dec 31, 2019·2 cites·17 claims
- 2280US2025347990A1Methods and systems to determine shapes for semiconductor or flat panel display fabricationD2S INC·Filed 2025·Application pending·0 cites
- 2379US12387029B2Computing parasitic values for semiconductor designsD2S INC·Filed 2022·Granted Aug 12, 2025·0 cites·20 claims
- 2478US12499301B2Computing parasitic values for semiconductor designsD2S INC·Filed 2022·Granted Dec 16, 2025·0 cites·20 claims
- 2578US12488175B2Methods and systems to determine parasitics for semiconductor or flat panel display fabricationD2S INC·Filed 2022·Granted Dec 2, 2025·0 cites·17 claims
- 2677US2025356102A1Dynamic computation of tile size for parasitics extractionD2S INC·Filed 2025·Application pending·0 cites
- 2776US2025356098A1Tiling of layout for parasitics extractionD2S INC·Filed 2025·Application pending·0 cites
- 2876US2025356100A1Iterative parasitics extraction for interconnect segments in different tilesD2S INC·Filed 2025·Application pending·0 cites
- 2976US2025356101A1Parasitics extraction for interconnect segments in 3d regionsD2S INC·Filed 2025·Application pending·0 cites
- 3076US2025356099A1Computation of parasitic values for interconnect segmentsD2S INC·Filed 2025·Application pending·0 cites
- 3173US10380297B2Integrated circuit design using generation and instantiation of circuit stencilsSYNOPSYS INC·Filed 2017·Granted Aug 13, 2019·1 cites·20 claims
- 3273US2023385513A1Using machine trained network during routing to perform parasitic extraction for an ic designD2S INC·Filed 2023·Application pending·0 cites
- 3373US2024119214A1Using a machine trained network during routing to account for opc costD2S INC·Filed 2023·Application pending·0 cites
- 3473US2023351089A1Using a machine trained network during routing to account for opc costD2S INC·Filed 2023·Application pending·0 cites
- 3573US2023351087A1Using machine trained network during routing to modify locations of vias in an ic designD2S INC·Filed 2023·Application pending·0 cites
- 3673US2023351088A1Using machine trained network during routing to modify locations of vias in an ic designD2S INC·Filed 2023·Application pending·0 cites
- 3773US2023385514A1Using machine trained network during routing to modify locations of vias in an ic designD2S INC·Filed 2023·Application pending·0 cites
- 3870US12475283B2Generating and display an animation of a predicted overlap shape in an IC designD2S INC·Filed 2022·Granted Nov 18, 2025·0 cites·20 claims
- 3961US10796062B2Full-custom voltage-dependent design rules (VDRC) flowSYNOPSYS INC·Filed 2018·Granted Oct 6, 2020·1 cites·53 claims
- 4060US10242135B2Testbench chaining for multiple blocks in hierarchical circuit designSYNOPSYS INC·Filed 2017·Granted Mar 26, 2019·1 cites·20 claims
- 4154US2023168660A1Based on multiple manufacturing process variations, producing multiple contours representing predicted shapes of an ic design componentD2S INC·Filed 2022·Application pending·0 cites
- 4250US2023092665A1Using a machine-trained network to perform physical designD2S INC·Filed 2022·Application pending·0 cites
- 4350US2023267265A1Using machine-trained network to perform drc checkD2S INC·Filed 2023·Application pending·0 cites
- 4450US2023359804A1Training machine-trained network to perform drc checkD2S INC·Filed 2023·Application pending·0 cites
- 4545US2023205972A1Computing and displaying a predicted overlap shape in an ic design based on predicted misalignment of metal layersD2S INC·Filed 2022·Application pending·0 cites
- 4644US10242139B2Scheme and design markup language for interoperability of electronic design application tool and browserSYNOPSYS INC·Filed 2017·Granted Mar 26, 2019·0 cites·20 claims
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