Inventor

SIU MING Y

US54 patents

⚠️ This page may combine multiple inventors who share the name “SIU MING Y”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SIU MING Y

NVIDIA CORP

Single interconnect providing read and write access to a memory shared by concurrent threads

Multipurpose functional unit with multiply-add and format conversion pipeline

Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators

Multipurpose functional unit with single-precision and double-precision operations

Generalized acceleration of matrix multiply accumulate operations

Multipurpose arithmetic functional unit

Multi-purpose floating point and integer multiply-add functional unit with multiplication-comparison test addition and exponent pipelines

Managing data sparsity for neural networks

Multipurpose functional unit with double-precision and filtering operations

Operand collector architecture

Register file allocation

Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q&lt;P)

Simulating multiported memories using lower port count memories

High-speed function approximation

Generalized acceleration of matrix multiply accumulate operations

Programmable graphics processor for multithreaded execution of programs

Multipurpose functional unit with multiplication pipeline, addition pipeline, addition pipeline and logical test pipeline capable of performing integer multiply-add operations

Cooperative thread array reduction and scan operations

Generalized acceleration of matrix multiply accumulate operations

Programmable graphics processor for multithreaded execution of programs

Compression techniques for data structures suitable for artificial neural networks

Approach to power reduction in floating-point operations

Cooperative thread array reduction and scan operations

Inline data inspection for workload simplification

Generalized acceleration of matrix multiply accumulate operations

Inline data inspection for workload simplification

Generalized acceleration of matrix multiply accumulate operations

Generalized acceleration of matrix multiply accumulate operations

Generalized acceleration of matrix multiply accumulate operations

Generalized acceleration of matrix multiply accumulate operations

Inline data inspection for workload simplification

Techniques for efficiently operating a processing system based on energy characteristics of instructions and machine learning

Decompression techniques for processing compressed data suitable for artificial neural networks

Inline data inspection for workload simplification

Providing hints to an execution unit to prepare for predicted subsequent arithmetic operations

COON BRETT W

Shared memory with parallel access and access conflict resolution mechanism

Scoreboard having size indicators for tracking sequential destination register usage in a multi-threaded processor

Shared single-access memory with management of multiple parallel requests

Shared single-access memory with management of multiple parallel requests

LINDHOLM JOHN ERIK

Programmable graphics processor for multithreaded execution of programs

Programmable graphics processor for multithreaded execution of programs

Programmable graphics processor for multithreaded execution of programs

FAHS BRIAN

Opcode-specified predicatable warp post-synchronization

Cooperative thread array reduction and scan operations

MINKIN ALEXANDER L

Cache miss processing using a defer/replay mechanism

OBERMAN STUART F

Multipurpose arithmetic functional unit

OBERMAN STUART

Fused multiply-add functional unit

SHEBANOW MICHAEL C

Trap handler architecture for a parallel processing unit

QIU XIAOGANG

Reordering operands assigned to each one of read request ports concurrently accessing multibank register file to avoid bank conflict

FIYAK MICHAEL

Fast mapping table register file allocation algorithm for SIMT processors

Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q<P)