Inventor · disambiguated record
Luc Burgun
Also filed as: BURGUN LUC · BURGUN LUC M
5 granted patents·2 pending applications·280 citations·filing 1996–2009
85Inventor score
Top patents by PatentIndex Score
7 records- 0177US6240376B1Method and apparatus for gate-level simulation of synthesized register transfer level designs with source-level debuggingMENTOR GRAPHICS CORP·Filed 1998·Granted May 29, 2001·94 cites·33 claims
- 0272US6336087B2Method and apparatus for gate-level simulation of synthesized register transfer level design with source-level debuggingFiled 1998·Granted Jan 1, 2002·80 cites·18 claims
- 0361US6301553B1Method and apparatus for removing timing hazards in a circuit designFiled 1998·Granted Oct 9, 2001·48 cites·25 claims
- 0459US5801955AMethod and apparatus for removing timing hazards in a circuit designMENTOR GRAPHICS CORP·Filed 1996·Granted Sep 1, 1998·32 cites·26 claims
- 0554US5831866AMethod and apparatus for removing timing hazards in a circuit designMENTOR GRAPHICS CORP·Filed 1997·Granted Nov 3, 1998·26 cites·23 claims
- 0648US2010161306A1Method and system for emulating a design under test associated with a test environmentEMULATION AND VERIFICATION ENG·Filed 2009·Application pending·0 cites
- 0732US2004111252A1Method and system for emulating a design under test associated with a test environmentEMULATION AND VERIFICATION ENG·Filed 2003·Application pending·0 cites
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