Inventor · disambiguated record
Michael C. Smayling
Also filed as: SMAYLING MICHAEL · SMAYLING MICHAEL C
227 granted patents·20 pending applications·12,653 citations·filing 1979–2020
99Inventor score
Files withTEXAS INSTRUMENTS INC85TELA INNOVATIONS INC66BECKER SCOTT T49MULTIBEAM CORP20SMAYLING MICHAEL C13
Top patents by PatentIndex Score
247 records- 0199US9443947B2Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the sameTELA INNOVATIONS INC·Filed 2015·Granted Sep 13, 2016·28 cites·30 claims
- 0299US9425273B2Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the sameTELA INNOVATIONS INC·Filed 2015·Granted Aug 23, 2016·24 cites·30 claims
- 0399US9425272B2Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the sameTELA INNOVATIONS INC·Filed 2015·Granted Aug 23, 2016·24 cites·30 claims
- 0499US8756551B2Methods for designing semiconductor device with dynamic array sectionBECKER SCOTT T·Filed 2011·Granted Jun 17, 2014·60 cites·29 claims
- 0599US8667443B2Integrated circuit cell library for multiple patterningSMAYLING MICHAEL C·Filed 2008·Granted Mar 4, 2014·94 cites·26 claims
- 0699US8436400B2Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different lengthBECKER SCOTT T·Filed 2009·Granted May 7, 2013·87 cites·32 claims
- 0799US8356268B2Integrated circuit device including dynamic array section with gate level having linear conductive features on at least three side-by-side lines and uniform line end spacingsTELA INNOVATIONS INC·Filed 2011·Granted Jan 15, 2013·129 cites·29 claims
- 0899US8283701B2Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halosBECKER SCOTT T·Filed 2011·Granted Oct 9, 2012·110 cites·43 claims
- 0999US8264008B2Semiconductor device including transistor forming linear shapes including gate portions and extending portions of different sizeBECKER SCOTT T·Filed 2009·Granted Sep 11, 2012·107 cites·38 claims
- 1099US8264007B2Semiconductor device including at least six transistor forming linear shapes including at least two different gate contact connection distancesBECKER SCOTT T·Filed 2009·Granted Sep 11, 2012·109 cites·46 claims
- 1199US8264009B2Semiconductor device with linearly restricted gate level region including four transistors of first type and four transistors of second type with gate defining shapes of different lengthBECKER SCOTT T·Filed 2009·Granted Sep 11, 2012·107 cites·49 claims
- 1299US8258550B2Semiconductor device including at least six transistor forming linear shapes including at least two transistor forming linear shapes having different extension distances beyond gate contactBECKER SCOTT T·Filed 2009·Granted Sep 4, 2012·115 cites·48 claims
- 1399US8258548B2Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region with restricted gate contact placement over separating non-diffusion regionBECKER SCOTT T·Filed 2009·Granted Sep 4, 2012·108 cites·50 claims
- 1499US8258552B2Semiconductor device including at least six transistor forming linear shapes with at least two transistor forming linear shapes having offset endsBECKER SCOTT T·Filed 2009·Granted Sep 4, 2012·119 cites·49 claims
- 1599US8258549B2Semiconductor device including two transistors of first type having gates formed by conductors of different length respectively aligned with two transistors of second type having gates formed by conductors of different lengthBECKER SCOTT T·Filed 2009·Granted Sep 4, 2012·110 cites·50 claims
- 1699US8258551B2Semiconductor device with gate level including transistors of first type and transistors of second type with corresponding gate contact placement restrictionBECKER SCOTT T·Filed 2009·Granted Sep 4, 2012·108 cites·50 claims
- 1799US8258547B2Semiconductor device with linearly restricted gate level region including two transistors of first type and two transistors of second type with offset gate contactsBECKER SCOTT T·Filed 2009·Granted Sep 4, 2012·114 cites·36 claims
- 1899US8253172B2Semiconductor device with linearly restricted gate level region including four serially connected transistors of first type and four serially connected transistors of second type separated by non-diffusion regionBECKER SCOTT T·Filed 2009·Granted Aug 28, 2012·111 cites·47 claims
- 1999US8253173B2Semiconductor device with gate level including four transistors of first type and four transistors of second type separated by non-diffusion region and having at least two gate contacts positioned outside separating non-diffusion regionBECKER SCOTT T·Filed 2009·Granted Aug 28, 2012·109 cites·47 claims
- 2099US8217428B2Integrated circuit including gate electrode level region including at least three linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different typeBECKER SCOTT T·Filed 2009·Granted Jul 10, 2012·114 cites·55 claims
- 2199US8207053B2Electrodes of transistors with at least two linear-shaped conductive structures of different lengthBECKER SCOTT T·Filed 2009·Granted Jun 26, 2012·103 cites·56 claims
- 2299US8198656B2Integrated circuit including gate electrode level region including at least four linear-shaped conductive structures of equal length having aligned ends and positioned at equal pitch and forming multiple gate electrodes of transistors of different typeBECKER SCOTT T·Filed 2009·Granted Jun 12, 2012·103 cites·55 claims
- 2399US8138525B2Integrated circuit including at least three linear-shaped conductive structures of different length each forming gate of different transistorBECKER SCOTT T·Filed 2009·Granted Mar 20, 2012·108 cites·42 claims
- 2499US8134185B2Integrated circuit having gate electrode level region including at least seven linear-shaped conductive structures at equal pitch including linear-shaped conductive structure forming transistors of two different types and at least three linear-shaped conductive structures having aligned endsBECKER SCOTT T·Filed 2009·Granted Mar 13, 2012·108 cites·50 claims
- 2599US8134184B2Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portionBECKER SCOTT T·Filed 2009·Granted Mar 13, 2012·177 cites·51 claims
- 2699US8134183B2Integrated circuit including linear-shaped conductive structures that have gate portions and extending portions of different sizeBECKER SCOTT T·Filed 2009·Granted Mar 13, 2012·114 cites·36 claims
- 2799US8134186B2Integrated circuit including at least three linear-shaped conductive structures at equal pitch including linear-shaped conductive structure having non-gate portion length greater than gate portion lengthBECKER SCOTT T·Filed 2009·Granted Mar 13, 2012·108 cites·44 claims
- 2899US8129750B2Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two linear-shaped conductive structures of different lengthBECKER SCOTT T·Filed 2009·Granted Mar 6, 2012·125 cites·50 claims
- 2999US8129757B2Integrated circuit including at least six linear-shaped conductive structive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different lengthBECKER SCOTT T·Filed 2009·Granted Mar 6, 2012·110 cites·42 claims
- 3099US8129754B2Integrated circuit with gate electrode level including at least six linear-shaped conductive structures forming gate electrodes of transisters with at least one pair of linear-shaped conductive structures having offset endsBECKER SCOTT T·Filed 2009·Granted Mar 6, 2012·112 cites·48 claims
- 3199US8129756B2Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes of transistors with at least two different extension distances beyond conductive contacting structuresBECKER SCOTT T·Filed 2009·Granted Mar 6, 2012·110 cites·46 claims
- 3299US8129751B2Integrated circuit including at least six linear-shaped conductive structures forming gate electrodes and including four conductive contacting structures having at least two different connection distancesBECKER SCOTT T·Filed 2009·Granted Mar 6, 2012·111 cites·44 claims
- 3399US8129752B2Integrated circuit including a linear-shaped conductive structure forming one gate electrode and having length greater than or equal to one-half the length of linear-shaped conductive structure forming two gate electrodesBECKER SCOTT T·Filed 2009·Granted Mar 6, 2012·111 cites·44 claims
- 3499US8129755B2Integrated circuit with gate electrode level including at least four linear-shaped conductive structures of equal length and equal pitch with linear-shaped conductive structure forming one transistorBECKER SCOTT T·Filed 2009·Granted Mar 6, 2012·110 cites·41 claims
- 3599US8129819B2Method of fabricating integrated circuit including at least six linear-shaped conductive structures at equal pitch including at least two linear-shaped conductive structures having non-gate portions of different lengthBECKER SCOTT T·Filed 2009·Granted Mar 6, 2012·105 cites·44 claims
- 3699US8110854B2Integrated circuit device with linearly defined gate electrode level region and shared diffusion region of first type connected to shared diffusion region of second type through at least two interconnect levelsBECKER SCOTT T·Filed 2009·Granted Feb 7, 2012·118 cites·40 claims
- 3799US8101975B2Integrated circuit device with gate level region including non-gate linear conductive segment positioned within 965 nanometers of four transistors of first type and four transistors of second typeBECKER SCOTT T·Filed 2009·Granted Jan 24, 2012·124 cites·36 claims
- 3899US8089098B2Integrated circuit device and associated layout including linear gate electrodes of different transistor types next to linear-shaped non-gate conductive segmentBECKER SCOTT T·Filed 2009·Granted Jan 3, 2012·129 cites·31 claims
- 3999US8089099B2Integrated circuit device and associated layout including gate electrode level region of 965 NM radius with linear-shaped conductive segments on fixed pitchBECKER SCOTT T·Filed 2009·Granted Jan 3, 2012·129 cites·45 claims
- 4099US8089102B2Method for fabricating integrated circuit having three or more linear-shaped gate electrode level conductive segments of both equal length and equal pitchBECKER SCOTT T·Filed 2009·Granted Jan 3, 2012·130 cites·38 claims
- 4199US8089104B2Integrated circuit with gate electrode level region including multiple linear-shaped conductive structures forming gate electrodes of transistors and including uniformity extending portions of different sizeBECKER SCOTT T·Filed 2009·Granted Jan 3, 2012·125 cites·38 claims
- 4299US8089100B2Integrated circuit with gate electrode level region including at least four linear-shaped conductive structures forming gate electrodes of transistors and including extending portions of at least two different sizesBECKER SCOTT T·Filed 2009·Granted Jan 3, 2012·134 cites·35 claims
- 4399US8088679B2Method for fabricating integrated circuit with gate electrode level portion including at least two complementary transistor forming linear conductive segments and at least one non-gate linear conductive segmentBECKER SCOTT T·Filed 2009·Granted Jan 3, 2012·126 cites·34 claims
- 4499US8088682B2Method for fabricating integrated circuit with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate levelBECKER SCOTT T·Filed 2009·Granted Jan 3, 2012·126 cites·45 claims
- 4599US8089101B2Integrated circuit device with gate electrode level region including two side-by-side ones of at least three linear-shaped conductive structures electrically connected to each other through non-gate levelBECKER SCOTT T·Filed 2009·Granted Jan 3, 2012·130 cites·43 claims
- 4699US8088681B2Method for fabricating integrated circuit including separated diffusion regions of different type each having four gate electrodes with each of two complementary gate electrode pairs formed from respective linear condcutive segmentBECKER SCOTT T·Filed 2009·Granted Jan 3, 2012·126 cites·46 claims
- 4799US8089103B2Integrated circuit device with gate level region including at least three linear-shaped conductive segments having offset line ends and forming three transistors of first type and one transistor of second typeBECKER SCOTT T·Filed 2009·Granted Jan 3, 2012·129 cites·34 claims
- 4899US8088680B2Method for fabricating integrated circuit having at least three linear-shaped gate electrode level conductive features of equal length positioned side-by-side at equal pitchBECKER SCOTT T·Filed 2009·Granted Jan 3, 2012·126 cites·49 claims
- 4999US8072003B2Integrated circuit device and associated layout including two pairs of co-aligned complementary gate electrodes with offset gate contact structuresBECKER SCOTT T·Filed 2009·Granted Dec 6, 2011·111 cites·37 claims
- 5099US8058671B2Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitchBECKER SCOTT T·Filed 2009·Granted Nov 15, 2011·146 cites·47 claims
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