Inventor
HARRIMAN DAVID
US50 patents
⚠️ This page may combine multiple inventors who share the name “HARRIMAN DAVID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
34 patentsUS7536473B2May 19, 2009
General input/output architecture, protocol and related methods to implement flow control
INTEL CORP106 citations99
US7251704B2Jul 31, 2007
Store and forward switch device, system and method
INTEL CORP71 citations98
US7231486B2Jun 12, 2007
General input/output architecture, protocol and related methods to support legacy interrupts
INTEL CORP85 citations98
US6691192B2Feb 10, 2004
Enhanced general input/output architecture and related methods for establishing virtual channels therein
INTEL CORP114 citations98
US7152128B2Dec 19, 2006
General input/output architecture, protocol and related methods to manage data integrity
INTEL CORP85 citations97
US8819306B2Aug 26, 2014
General input/output architecture with PCI express protocol with credit-based flow control
INTEL CORP20 citations96
US7099318B2Aug 29, 2006
Communicating message request transaction types between agents in a computer system using multiple message groups
INTEL CORP35 citations96
US6944617B2Sep 13, 2005
Communicating transaction types between agents in a computer system using packet headers including an extended type/extended length field
INTEL CORP59 citations96
US7949794B2May 24, 2011
PCI express enhancements and extensions
INTEL CORP41 citations95
US9736071B2Aug 15, 2017
General input/output architecture, protocol and related methods to implement flow control
INTEL CORP9 citations93
US9565106B2Feb 7, 2017
General input/output architecture, protocol and related methods to implement flow control
INTEL CORP7 citations93
US9088495B2Jul 21, 2015
General input/output architecture, protocol and related methods to implement flow control
INTEL CORP10 citations93
US9049125B2Jun 2, 2015
General input/output architecture, protocol and related methods to implement flow control
INTEL CORP7 citations93
US7769883B2Aug 3, 2010
Communicating message request transaction types between agents in a computer system using multiple message groups
INTEL CORP24 citations93
US7581026B2Aug 25, 2009
Communicating transaction types between agents in a computer system using packet headers including format and type fields
INTEL CORP23 citations93
US7184399B2Feb 27, 2007
Method for handling completion packets with a non-successful completion status
INTEL CORP25 citations93
US7177971B2Feb 13, 2007
General input/output architecture, protocol and related methods to provide isochronous channels
INTEL CORP47 citations93
US6993611B2Jan 31, 2006
Enhanced general input/output architecture and related methods for establishing virtual channels therein
INTEL CORP39 citations93
US7930566B2Apr 19, 2011
PCI express enhancements and extensions
INTEL CORP13 citations92
US7899943B2Mar 1, 2011
PCI express enhancements and extensions
INTEL CORP16 citations92
US5974571AOct 26, 1999
Method and apparatus for avoiding deadlock in the issuance of commands that are reordered and require data movement according to an original command order
INTEL CORP25 citations92
US7353313B2Apr 1, 2008
General input/output architecture, protocol and related methods to manage data integrity
INTEL CORP15 citations91
US9860173B2Jan 2, 2018
General input/output architecture, protocol and related methods to implement flow control
INTEL CORP4 citations84
US9071528B2Jun 30, 2015
General input/output architecture, protocol and related methods to implement flow control
INTEL CORP6 citations84
US7039047B1May 2, 2006
Virtual wire signaling
INTEL CORP7 citations74
US10503684B2Dec 10, 2019
Multiple uplink port devices
INTEL CORP4 citations73
US9836424B2Dec 5, 2017
General input/output architecture, protocol and related methods to implement flow control
INTEL CORP5 citations73
US11657015B2May 23, 2023
Multiple uplink port devices
INTEL CORP0 citations63
US10884971B2Jan 5, 2021
Communicating a message request transaction to a logical device
INTEL CORP0 citations63
US10581545B2Mar 3, 2020
Two-wire link for time-multiplexed power and data transmission to multiple devices
INTEL CORP1 citations63
US9602408B2Mar 21, 2017
General input/output architecture, protocol and related methods to implement flow control
INTEL CORP1 citations63
US10360171B2Jul 23, 2019
Communicating a message request transaction to a logical device
INTEL CORP0 citations52
US7191375B2Mar 13, 2007
Method and apparatus for signaling an error condition to an agent not expecting a completion
INTEL CORP0 citations52
US12314397B2May 27, 2025
Support of PCIe device with multiple security policies
INTEL CORP0 citations51
AJANOVIC JASMIN
10 patentsUS8230120B2Jul 24, 2012
PCI express enhancements and extensions
AJANOVIC JASMIN21 citations96
US8566473B2Oct 22, 2013
General input/output architecture, protocol and related methods to implement flow control
AJANOVIC JASMIN16 citations93
US8555101B2Oct 8, 2013
PCI express enhancements and extensions
AJANOVIC JASMIN7 citations92
US8549183B2Oct 1, 2013
PCI express enhancements and extensions
AJANOVIC JASMIN8 citations92
US8473642B2Jun 25, 2013
PCI express enhancements and extensions including device window caching
AJANOVIC JASMIN6 citations92
US8447888B2May 21, 2013
PCI express enhancements and extensions
AJANOVIC JASMIN8 citations92
US8230119B2Jul 24, 2012
PCI express enhancements and extensions
AJANOVIC JASMIN14 citations92
US8099523B2Jan 17, 2012
PCI express enhancements and extensions including transactions having prefetch parameters
AJANOVIC JASMIN16 citations92
US8073981B2Dec 6, 2011
PCI express enhancements and extensions
AJANOVIC JASMIN14 citations92
US8793404B2Jul 29, 2014
Atomic operations
AJANOVIC JASMIN5 citations84
HARRIMAN DAVID
3 patentsUS8108584B2Jan 31, 2012
Use of completer knowledge of memory region ordering requirements to modify transaction attributes
HARRIMAN DAVID6 citations83
US8582602B2Nov 12, 2013
Communicating a message request transaction to a logical device
HARRIMAN DAVID3 citations61
US8307144B2Nov 6, 2012
Use of completer knowledge of memory region ordering requirements to modify transaction attributes
HARRIMAN DAVID0 citations51