Inventor · disambiguated record
Sridhar Lakshmanamurthy
Also filed as: LAKSHMANAMURTHY SRIDHAR
52 granted patents·12 pending applications·579 citations·filing 1996–2023
98Inventor score
Top patents by PatentIndex Score
64 records- 0197US7437510B2Instruction-assisted cache management for efficient use of cache and memoryINTEL CORP·Filed 2005·Granted Oct 14, 2008·78 cites·22 claims
- 0292US7653069B2Two stage queue arbitrationINTEL CORP·Filed 2005·Granted Jan 26, 2010·29 cites·23 claims
- 0391US7366865B2Enqueueing entries in a packet queue referencing packetsINTEL CORP·Filed 2004·Granted Apr 29, 2008·67 cites·42 claims
- 0491US7360031B2Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spacesINTEL CORP·Filed 2005·Granted Apr 15, 2008·30 cites·22 claims
- 0590US8929373B2Sending packets with expanded headersLAKSHMANAMURTHY SRIDHAR·Filed 2011·Granted Jan 6, 2015·13 cites·18 claims
- 0690US8874976B2Providing error handling support to legacy devicesLAKSHMANAMURTHY SRIDHAR·Filed 2011·Granted Oct 28, 2014·13 cites·11 claims
- 0790US8711875B2Aggregating completion messages in a sideband interfaceLAKSHMANAMURTHY SRIDHAR·Filed 2011·Granted Apr 29, 2014·12 cites·16 claims
- 0889US8713234B2Supporting multiple channels of a single interfaceLAKSHMANAMURTHY SRIDHAR·Filed 2011·Granted Apr 29, 2014·12 cites·20 claims
- 0988US8775700B2Issuing requests to a fabricLAKSHMANAMURTHY SRIDHAR·Filed 2011·Granted Jul 8, 2014·10 cites·10 claims
- 1088US8713240B2Providing multiple decode options for a system-on-chip (SoC) fabricLAKSHMANAMURTHY SRIDHAR·Filed 2011·Granted Apr 29, 2014·10 cites·21 claims
- 1187US9053251B2Providing a sideband message interface for system on a chip (SoC)ADLER ROBERT P·Filed 2011·Granted Jun 9, 2015·14 cites·19 claims
- 1284US8805926B2Common idle state, active state and credit management for an interfaceLAKSHMANAMURTHY SRIDHAR·Filed 2011·Granted Aug 12, 2014·7 cites·12 claims
- 1383US9075929B2Issuing requests to a fabricINTEL CORP·Filed 2014·Granted Jul 7, 2015·5 cites·23 claims
- 1482US7505410B2Method and apparatus to support efficient check-point and role-back operations for flow-controlled queues in network devicesINTEL CORP·Filed 2005·Granted Mar 17, 2009·11 cites·16 claims
- 1581US9916876B2Ultra low power architecture to support always on path to memoryINTEL CORP·Filed 2014·Granted Mar 13, 2018·6 cites·22 claims
- 1681US7525958B2Apparatus and method for two-stage packet classification using most specific filter matching and transport level sharingINTEL CORP·Filed 2004·Granted Apr 28, 2009·31 cites·50 claims
- 1779US9658978B2Providing multiple decode options for a system-on-chip (SoC) fabricINTEL CORP·Filed 2014·Granted May 23, 2017·4 cites·30 claims
- 1879US8370558B2Apparatus and method to merge and align data from distributed memory controllersINTEL CORP·Filed 2009·Granted Feb 5, 2013·8 cites·19 claims
- 1979US7698498B2Memory controller with bank sorting and schedulingINTEL CORP·Filed 2005·Granted Apr 13, 2010·15 cites·15 claims
- 2077US8087024B2Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cacheLAKSHMANAMURTHY SRIDHAR·Filed 2008·Granted Dec 27, 2011·7 cites·5 claims
- 2176US7412551B2Methods and apparatus for supporting programmable burst management schemes on pipelined busesINTEL CORP·Filed 2004·Granted Aug 12, 2008·25 cites·26 claims
- 2276US7308526B2Memory controller module having independent memory controllers for different memory typesINTEL CORP·Filed 2004·Granted Dec 11, 2007·24 cites·24 claims
- 2374US7512729B2Method and apparatus for a high efficiency two-stage rotating priority arbiter with predictable arbitration latencyINTEL CORP·Filed 2005·Granted Mar 31, 2009·8 cites·21 claims
- 2471US9213666B2Providing a sideband message interface for system on a chip (SoC)INTEL CORP·Filed 2014·Granted Dec 15, 2015·2 cites·24 claims
- 2571US7426610B2On-device packet descriptor cacheINTEL CORP·Filed 2005·Granted Sep 16, 2008·4 cites·21 claims
- 2669US7200699B2Scalable, two-stage round robin arbiter with re-circulation and bounded latencyINTEL CORP·Filed 2004·Granted Apr 3, 2007·15 cites·30 claims
- 2767US5903916AComputer memory subsystem and method for performing opportunistic write data transfers during an access latency period within a read or refresh operationINTEL CORP·Filed 1996·Granted May 11, 1999·50 cites·15 claims
- 2866US10164880B2Sending packets with expanded headersINTEL CORP·Filed 2014·Granted Dec 25, 2018·1 cites·22 claims
- 2966US9448870B2Providing error handling support to legacy devicesINTEL CORP·Filed 2014·Granted Sep 20, 2016·1 cites·23 claims
- 3065US9489329B2Supporting multiple channels of a single interfaceINTEL CORP·Filed 2014·Granted Nov 8, 2016·1 cites·24 claims
- 3165US7251219B2Method and apparatus to communicate flow control information in a duplex network processor systemINTEL CORP·Filed 2002·Granted Jul 31, 2007·10 cites·8 claims
- 3264US7185153B2Packet assemblyINTEL CORP·Filed 2003·Granted Feb 27, 2007·8 cites·17 claims
- 3363US12417047B2Heterogeneous ML accelerator cluster with flexible system resource balanceGOOGLE LLC·Filed 2023·Granted Sep 16, 2025·0 cites·20 claims
- 3463US11372674B2Method, apparatus and system for handling non-posted memory write transactions in a fabricINTEL CORP·Filed 2020·Granted Jun 28, 2022·0 cites·26 claims
- 3562US7313140B2Method and apparatus to assemble data segments into full packets for efficient packet-based classificationINTEL CORP·Filed 2002·Granted Dec 25, 2007·8 cites·20 claims
- 3660US7324520B2Method and apparatus to process switch trafficINTEL CORP·Filed 2002·Granted Jan 29, 2008·6 cites·17 claims
- 3759US7103821B2Method and apparatus for improving network router line rate performance by an improved system for error checkingINTEL CORP·Filed 2002·Granted Sep 5, 2006·7 cites·28 claims
- 3858US7480781B2Apparatus and method to merge and align data from distributed memory controllersINTEL CORP·Filed 2004·Granted Jan 20, 2009·5 cites·6 claims
- 3957US9064051B2Issuing requests to a fabricINTEL CORP·Filed 2014·Granted Jun 23, 2015·0 cites·17 claims
- 4057US7210008B2Memory controller for padding and stripping data in response to read and write commandsINTEL CORP·Filed 2003·Granted Apr 24, 2007·5 cites·9 claims
- 4156US9270576B2Aggregating completion messages in a sideband interfaceINTEL CORP·Filed 2014·Granted Feb 23, 2016·0 cites·22 claims
- 4254US9753875B2Systems and an apparatus with a sideband interface interconnecting agents with at least one routerINTEL CORP·Filed 2016·Granted Sep 5, 2017·0 cites·18 claims
- 4354US9122815B2Common idle state, active state and credit management for an interfaceINTEL CORP·Filed 2014·Granted Sep 1, 2015·0 cites·27 claims
- 4453US10846126B2Method, apparatus and system for handling non-posted memory write transactions in a fabricINTEL CORP·Filed 2016·Granted Nov 24, 2020·0 cites·20 claims
- 4553US7707266B2Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unitINTEL CORP·Filed 2004·Granted Apr 27, 2010·5 cites·26 claims
- 4653US7337371B2Method and apparatus to handle parity errors in flow control channelsINTEL CORP·Filed 2003·Granted Feb 26, 2008·2 cites·27 claims
- 4752US7158438B2Network packet buffer allocation optimization in memory bank systemsINTEL CORP·Filed 2005·Granted Jan 2, 2007·2 cites·21 claims
- 4852US2006277126A1Ring credit managementINTEL CORP·Filed 2005·Application pending·0 cites
- 4951US7213099B2Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matchesINTEL CORP·Filed 2003·Granted May 1, 2007·2 cites·22 claims
- 5050US7340570B2Engine for comparing a key with rules having high and low values defining a rangeINTEL CORP·Filed 2004·Granted Mar 4, 2008·2 cites·36 claims
Showing the top 50 of 64 patent records by PatentIndex Score.
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