Inventor · disambiguated record
Charles A. Cornell
Also filed as: CORNELL CHARLES · CORNELL CHARLES A
10 granted patents·151 citations·filing 2002–2018
90Inventor score
Files withCYPRESS SEMICONDUCTOR CORP6FREESCALE SEMICONDUCTOR INC2SAMSUNG ELECTRONICS CO LTD1TOWER SAMUEL J1
Top patents by PatentIndex Score
10 records- 0193US7583121B2Flip-flop having logic state retention during a power down mode and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Sep 1, 2009·40 cites·19 claims
- 0287US7176720B1Low duty cycle distortion differential to CMOS translatorCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Feb 13, 2007·38 cites·17 claims
- 0376US7239178B1Circuit and method for CMOS voltage level translationCYPRESS SEMICONDUCTOR CORP·Filed 2005·Granted Jul 3, 2007·9 cites·14 claims
- 0473US7826581B1Linearized digital phase-locked loop method for maintaining end of packet time linearityCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Nov 2, 2010·20 cites·21 claims
- 0573US7683697B2Circuitry and method for buffering a power mode control signalFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Mar 23, 2010·7 cites·20 claims
- 0670US6781465B1Method and apparatus for differential signal detectionCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Aug 24, 2004·17 cites·24 claims
- 0769US8289060B2Pulsed state retention power gating flip-flopTOWER SAMUEL J·Filed 2007·Granted Oct 16, 2012·8 cites·18 claims
- 0869US7394293B1Circuit and method for rapid power up of a differential output driverCYPRESS SEMICONDUCTOR CORP·Filed 2005·Granted Jul 1, 2008·6 cites·20 claims
- 0946US10607982B2Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cellSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Mar 31, 2020·0 cites·15 claims
- 1044US6683818B1Asynchronous random access memory with power optimizing clockCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Jan 27, 2004·6 cites·20 claims
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