Inventor · disambiguated record
Steven R. Durrill
Also filed as: DURRILL STEVEN · DURRILL STEVEN R · DURRILL STEVEN ROBERTS
10 granted patents·179 citations·filing 2009–2017
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
10 records- 0195US10289793B1System and method to generate schematics from layout-fabrics with a common cross-fabric modelCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·16 cites·20 claims
- 0295US9881120B1Method, system, and computer program product for implementing a multi-fabric mixed-signal design spanning across multiple design fabrics with electrical and thermal analysis awarenessCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jan 30, 2018·18 cites·20 claims
- 0395US9881119B1Methods, systems, and computer program product for constructing a simulation schematic of an electronic design across multiple design fabricsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jan 30, 2018·19 cites·21 claims
- 0493US10285276B1Method and apparatus to drive layout of arbitrary EM-coil through parametrized cellCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted May 7, 2019·17 cites·19 claims
- 0593US9449130B1Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 20, 2016·10 cites·20 claims
- 0693US9286421B1Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Mar 15, 2016·16 cites·20 claims
- 0791US9934354B1Methods, systems, and computer program product for implementing a layout-driven, multi-fabric schematic designCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Apr 3, 2018·15 cites·20 claims
- 0890US8521483B1Method and apparatus for concurrent design of modules across different design entry tools targeted to single simulationKUKAL TARANJIT·Filed 2010·Granted Aug 27, 2013·18 cites·27 claims
- 0989US8438524B1Hierarchical editing of printed circuit board pin assignmentKOHLI VIKAS·Filed 2009·Granted May 7, 2013·26 cites·24 claims
- 1089US8316342B1Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layoutKUKAL TARANJIT·Filed 2010·Granted Nov 20, 2012·24 cites·28 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →