Inventor · disambiguated record
Christopher H. Olson
Also filed as: OLSON CHRISTOPHER · OLSON CHRISTOPHER H · OLSON CHRISTOPHER HANS
83 granted patents·8 pending applications·1,900 citations·filing 1991–2021
99Inventor score
Top patents by PatentIndex Score
91 records- 0198US7795899B1Enabling on-chip features via efusesORACLE AMERICA INC·Filed 2009·Granted Sep 14, 2010·73 cites·20 claims
- 0297US7620821B1Processor including general-purpose and cryptographic functionality in which cryptographic operations are visible to user-specified softwareSUN MICROSYSTEMS INC·Filed 2005·Granted Nov 17, 2009·90 cites·22 claims
- 0395US8417961B2Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC)OLSON CHRISTOPHER H·Filed 2010·Granted Apr 9, 2013·31 cites·15 claims
- 0494US7478225B1Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Jan 13, 2009·100 cites·18 claims
- 0593US8671129B2System and method of bypassing unrounded results in a multiply-add pipeline unitBROOKS JEFFREY S·Filed 2011·Granted Mar 11, 2014·21 cites·20 claims
- 0693US7570760B1Apparatus and method for implementing a block cipher algorithmSUN MICROSYSTEMS INC·Filed 2004·Granted Aug 4, 2009·91 cites·27 claims
- 0792US6265831B1Plasma processing method and apparatus with control of rf biasLAM RES CORP·Filed 1999·Granted Jul 24, 2001·78 cites·19 claims
- 0890US8862861B2Suppressing branch prediction information update by branch instructions in incorrect speculative execution pathOLSON CHRISTOPHER H·Filed 2011·Granted Oct 14, 2014·14 cites·16 claims
- 0990US8654970B2Apparatus and method for implementing instruction support for the data encryption standard (DES) algorithmOLSON CHRISTOPHER H·Filed 2009·Granted Feb 18, 2014·21 cites·25 claims
- 1090US7320063B1Synchronization primitives for flexible scheduling of functional unit operationsSUN MICROSYSTEMS INC·Filed 2005·Granted Jan 15, 2008·23 cites·23 claims
- 1189US8555038B2Processor and method providing instruction support for instructions that utilize multiple register windowsOLSON CHRISTOPHER H·Filed 2010·Granted Oct 8, 2013·14 cites·18 claims
- 1289US7571284B1Out-of-order memory transactions in a fine-grain multithreaded/multi-core processorSUN MICROSYSTEMS INC·Filed 2004·Granted Aug 4, 2009·64 cites·22 claims
- 1388US8886920B2Associating tag to branch instruction to access array storing predicted target addresses for page crossing targets for comparison with resolved address at execution stageOLSON CHRISTOPHER H·Filed 2011·Granted Nov 11, 2014·12 cites·15 claims
- 1487US7684563B1Apparatus and method for implementing a unified hash algorithm pipelineSUN MICROSYSTEMS INC·Filed 2004·Granted Mar 23, 2010·49 cites·32 claims
- 1586US6361645B1Method and device for compensating wafer bias in a plasma processing chamberLAM RES CORP·Filed 1998·Granted Mar 26, 2002·83 cites·32 claims
- 1685US8832464B2Processor and method for implementing instruction support for hash algorithmsOLSON CHRISTOPHER H·Filed 2009·Granted Sep 9, 2014·14 cites·20 claims
- 1784US5758680AMethod and apparatus for pressure control in vacuum processorsLAM RES CORP·Filed 1996·Granted Jun 2, 1998·52 cites·21 claims
- 1882US8560814B2Thread fairness on a multi-threaded processor with multi-cycle cryptographic operationsGOLLA ROBERT T·Filed 2010·Granted Oct 15, 2013·7 cites·20 claims
- 1982US5961636ACheckpoint table for selective instruction flushing in a speculative execution unitIBM·Filed 1997·Granted Oct 5, 1999·99 cites·13 claims
- 2081US9086890B2Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicatedOLSON CHRISTOPHER H·Filed 2012·Granted Jul 21, 2015·6 cites·12 claims
- 2181US8356185B2Apparatus and method for local operand bypassing for cryptographic instructionsORACLE AMERICA INC·Filed 2009·Granted Jan 15, 2013·10 cites·20 claims
- 2281US8239440B2Processor which implements fused and unfused multiply-add instructions in a pipelined mannerBROOKS JEFFREY S·Filed 2008·Granted Aug 7, 2012·9 cites·16 claims
- 2380US7353364B1Apparatus and method for sharing a functional unit execution resource among a plurality of functional unitsSUN MICROSYSTEMS INC·Filed 2004·Granted Apr 1, 2008·32 cites·30 claims
- 2478US8438208B2Processor and method for implementing instruction support for multiplication of large operandsOLSON CHRISTOPHER H·Filed 2009·Granted May 7, 2013·8 cites·20 claims
- 2576US10180819B2Processing fixed and variable length numbersORACLE INT CORP·Filed 2016·Granted Jan 15, 2019·2 cites·20 claims
- 2676US8583902B2Instruction support for performing montgomery multiplicationOLSON CHRISTOPHER H·Filed 2010·Granted Nov 12, 2013·4 cites·20 claims
- 2776US5634103AMethod and system for minimizing branch misprediction penalties within a processorIBM·Filed 1995·Granted May 27, 1997·79 cites·18 claims
- 2875US8195923B2Methods and mechanisms to support multiple features for a number of opcodesSPRACKLEN LAWRENCE A·Filed 2009·Granted Jun 5, 2012·7 cites·20 claims
- 2975US7720219B1Apparatus and method for implementing a hash algorithm word bufferORACLE AMERICA INC·Filed 2004·Granted May 18, 2010·20 cites·36 claims
- 3075US5826070AApparatus and method for maintaining status flags and condition codes using a renaming technique in an out of order floating point execution unitIBM·Filed 1996·Granted Oct 20, 1998·75 cites·10 claims
- 3175US5392228AResult normalizer and method of operationMOTOROLA INC·Filed 1993·Granted Feb 21, 1995·67 cites·5 claims
- 3274US9747073B2Floating point unit with support for variable length numbersORACLE INT CORP·Filed 2014·Granted Aug 29, 2017·3 cites·3 claims
- 3373US8078942B2Register error correction of speculative data in an out-of-order processorJORDAN PAUL J·Filed 2007·Granted Dec 13, 2011·5 cites·19 claims
- 3472US7437538B1Apparatus and method for reducing execution latency of floating point operations having special case operandsSUN MICROSYSTEMS INC·Filed 2004·Granted Oct 14, 2008·16 cites·27 claims
- 3572US5880983AFloating point split multiply/add system which has infinite precisionIBM·Filed 1996·Granted Mar 9, 1999·64 cites·42 claims
- 3672US5822758AMethod and system for high performance dynamic and user programmable cache arbitrationIBM·Filed 1996·Granted Oct 13, 1998·65 cites·43 claims
- 3771US8195919B1Handling multi-cycle integer operations for a multi-threaded processorOLSON CHRISTOPHER H·Filed 2007·Granted Jun 5, 2012·5 cites·19 claims
- 3871US7099910B2Partitioned shifter for single instruction stream multiple data stream (SIMD) operationsSUN MICROSYSTEMS INC·Filed 2003·Granted Aug 29, 2006·18 cites·20 claims
- 3970US8977670B2Processor pipeline which implements fused and unfused multiply-add instructionsBROOKS JEFFREY S·Filed 2012·Granted Mar 10, 2015·2 cites·17 claims
- 4070US7711955B1Apparatus and method for cryptographic key expansionORACLE AMERICA INC·Filed 2004·Granted May 4, 2010·14 cites·27 claims
- 4169US9507564B2Processing fixed and variable length numbersORACLE INT CORP·Filed 2014·Granted Nov 29, 2016·2 cites·20 claims
- 4269US5241493AFloating point arithmetic unit with size efficient pipelined multiply-add architectureIBM·Filed 1991·Granted Aug 31, 1993·56 cites·13 claims
- 4368US7216216B1Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new windowSUN MICROSYSTEMS INC·Filed 2004·Granted May 8, 2007·13 cites·20 claims
- 4466US5384723AMethod and apparatus for floating point normalizationIBM·Filed 1994·Granted Jan 24, 1995·43 cites·14 claims
- 4565US10198260B2Processing instruction control transfer instructionsORACLE INT CORP·Filed 2016·Granted Feb 5, 2019·1 cites·20 claims
- 4665US7433912B1Multiplier structure supporting different precision multiplication operationsSUN MICROSYSTEMS INC·Filed 2004·Granted Oct 7, 2008·12 cites·21 claims
- 4763US9317286B2Apparatus and method for implementing instruction support for the camellia cipher algorithmOLSON CHRISTOPHER H·Filed 2009·Granted Apr 19, 2016·2 cites·16 claims
- 4863US8452831B2Apparatus and method for implementing hardware support for denormalized operands for floating-point divide operationsOLSON CHRISTOPHER H·Filed 2009·Granted May 28, 2013·2 cites·20 claims
- 4963US7523330B2Thread-based clock enabling in a multi-threaded processorSUN MICROSYSTEMS INC·Filed 2004·Granted Apr 21, 2009·8 cites·18 claims
- 5063US5957997AEfficient floating point normalization mechanismIBM·Filed 1997·Granted Sep 28, 1999·43 cites·20 claims
Showing the top 50 of 91 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →