Inventor · disambiguated record
Peichun Peter Liu
Also filed as: LIU PEICHUN · LIU PEICHUN P · LIU PEICHUN PETER
44 granted patents·6 pending applications·963 citations·filing 1994–2011
98Inventor score
Top patents by PatentIndex Score
50 records- 0196US6721874B1Method and system for dynamically shared completion table supporting multiple threads in a processing systemIBM·Filed 2000·Granted Apr 13, 2004·128 cites·23 claims
- 0294US7386636B2System and method for communicating command parameters between a processor and a memory flow controllerIBM·Filed 2005·Granted Jun 10, 2008·36 cites·22 claims
- 0393US5752260AHigh-speed, multiple-port, interleaved cache with arbitration of multiple access addressesIBM·Filed 1996·Granted May 12, 1998·117 cites·12 claims
- 0490US7590774B2Method and system for efficient context swappingTOSHIBA KK·Filed 2005·Granted Sep 15, 2009·29 cites·16 claims
- 0589US6820143B2On-chip data transfer in multi-processor systemIBM·Filed 2002·Granted Nov 16, 2004·58 cites·24 claims
- 0688US7500035B2Livelock resolution methodIBM·Filed 2006·Granted Mar 3, 2009·16 cites·20 claims
- 0784US7287103B2Method and apparatus for generating a mask value and command for extreme data rate memories utilizing error correction codesIBM·Filed 2005·Granted Oct 23, 2007·15 cites·20 claims
- 0884US7043579B2Ring-topology based multiprocessor data access busIBM·Filed 2002·Granted May 9, 2006·40 cites·21 claims
- 0984US5699288ACompare circuit for content-addressable memoriesIBM·Filed 1996·Granted Dec 16, 1997·59 cites·11 claims
- 1072US7698473B2Methods and apparatus for list transfers using DMA transfers in a multi-processor systemSONY COMPUTER ENTERTAINMENT INC·Filed 2005·Granted Apr 13, 2010·6 cites·25 claims
- 1171US7107376B2Systems and methods for bandwidth shapingTOSHIBA AMERICA ELECTRONIC·Filed 2004·Granted Sep 12, 2006·15 cites·31 claims
- 1269US7055004B2Pseudo-LRU for a locking cacheIBM·Filed 2003·Granted May 30, 2006·13 cites·24 claims
- 1368US7069390B2Implementation of a pseudo-LRU algorithm in a partitioned cacheIBM·Filed 2003·Granted Jun 27, 2006·14 cites·20 claims
- 1467US5668972AMethod and system for efficient miss sequence cache line allocation utilizing an allocation control cell state to enable a selected match lineIBM·Filed 1994·Granted Sep 16, 1997·47 cites·10 claims
- 1566US7243200B2Establishing command order in an out of order DMA command queueIBM·Filed 2004·Granted Jul 10, 2007·11 cites·17 claims
- 1665US8171448B2Structure for a livelock resolution circuitJOHNS CHARLES R·Filed 2008·Granted May 1, 2012·3 cites·18 claims
- 1764US8024489B2System for communicating command parameters between a processor and a memory flow controllerIBM·Filed 2008·Granted Sep 20, 2011·2 cites·20 claims
- 1864US7225277B2Proxy direct memory accessIBM·Filed 2003·Granted May 29, 2007·12 cites·24 claims
- 1963US5787478AMethod and system for implementing a cache coherency mechanism for utilization within a non-inclusive cache memory hierarchyIBM·Filed 1997·Granted Jul 28, 1998·43 cites·18 claims
- 2063US5640534AMethod and system for concurrent access in a data cache array utilizing multiple match line selection pathsIBM·Filed 1994·Granted Jun 17, 1997·42 cites·16 claims
- 2162US6931493B2Implementation of an LRU and MRU algorithm in a partitioned cacheIBM·Filed 2003·Granted Aug 16, 2005·8 cites·22 claims
- 2262US5623632ASystem and method for improving multilevel cache performance in a multiprocessing systemIBM·Filed 1995·Granted Apr 22, 1997·41 cites·16 claims
- 2359US6983387B2Microprocessor chip simultaneous switching current reduction method and apparatusIBM·Filed 2002·Granted Jan 3, 2006·6 cites·18 claims
- 2457US7657667B2Method to provide cache management commands for a DMA controllerIBM·Filed 2004·Granted Feb 2, 2010·5 cites·18 claims
- 2556US5805855AData cache array having multiple content addressable fields per cache lineIBM·Filed 1994·Granted Sep 8, 1998·27 cites·19 claims
- 2655US7861022B2Livelock resolutionIBM·Filed 2009·Granted Dec 28, 2010·0 cites·20 claims
- 2755US6961820B2System and method for identifying and accessing streaming data in a locked portion of a cacheIBM·Filed 2003·Granted Nov 1, 2005·4 cites·23 claims
- 2855US6822486B1Multiplexer methods and apparatusIBM·Filed 2003·Granted Nov 23, 2004·2 cites·19 claims
- 2955US5802567AMechanism for managing offset and aliasing conditions within a content-addressable memory-based cache memoryIBM·Filed 1996·Granted Sep 1, 1998·30 cites·10 claims
- 3052US7725618B2Memory barriers primitives in an asymmetric heterogeneous multiprocessor environmentIBM·Filed 2004·Granted May 25, 2010·2 cites·20 claims
- 3151US6202128B1Method and system for pre-fetch cache interrogation using snoop portIBM·Filed 1998·Granted Mar 13, 2001·24 cites·10 claims
- 3248US8483227B2Controlling bandwidth reservations method and apparatusASANO SHIGEHIRO·Filed 2003·Granted Jul 9, 2013·0 cites·6 claims
- 3347US8611368B2Controlling bandwidth reservations method and apparatusASANO SHIGEHIRO·Filed 2011·Granted Dec 17, 2013·0 cites·4 claims
- 3447US6510493B1Method and apparatus for managing cache line replacement within a computer systemIBM·Filed 1999·Granted Jan 21, 2003·18 cites·9 claims
- 3546US2006026308A1DMAC issue mechanism via streaming ID methodSONY COMPUTER ENTERTAINMENT INC·Filed 2004·Application pending·0 cites
- 3645US7231479B2Round robin selection logic improves area efficiency and circuit speedIBM·Filed 2003·Granted Jun 12, 2007·0 cites·11 claims
- 3745US5937429ACache memory having a selectable cache-line replacement scheme using cache-line registers in a ring configuration with a token indicatorIBM·Filed 1997·Granted Aug 10, 1999·20 cites·17 claims
- 3845US5761714ASingle-cycle multi-accessible interleaved cacheIBM·Filed 1996·Granted Jun 2, 1998·18 cites·15 claims
- 3945US2006015689A1Implementation and management of moveable buffers in cache systemSONY COMPUTER ENTERTAINMENT INC·Filed 2004·Application pending·0 cites
- 4045US2008065855A1DMAC Address Translation Miss Handling MechanismKING MATTHEW E·Filed 2006·Application pending·0 cites
- 4145US2008162823A1System and method for handling multiple aliased shadow register numbers to enhance lock acquisitionIBM·Filed 2007·Application pending·0 cites
- 4243US5890221AMethod and system for offset miss sequence handling in a data cache array having multiple content addressable field per cache line utilizing an MRU bitIBM·Filed 1994·Granted Mar 30, 1999·15 cites·12 claims
- 4341US6484251B1Updating condition status register based on instruction specific modification information in set/clear pair upon instruction commit in out-of-order processorIBM·Filed 1999·Granted Nov 19, 2002·12 cites·22 claims
- 4441US5905999ACache sub-array arbitrationIBM·Filed 1996·Granted May 18, 1999·13 cites·23 claims
- 4541US2009077322A1System and Method for Getllar Hit Cache Line Data Forward Via Data-Only Transfer Protocol Through BEB BusJOHNS CHARLES RAY·Filed 2007·Application pending·0 cites
- 4638US6041390AToken mechanism for cache-line replacement within a cache memory having redundant cache linesIBM·Filed 1996·Granted Mar 21, 2000·9 cites·14 claims
- 4734US2006023552A1Read/write methods for limited memory access applicationsIBM·Filed 2004·Application pending·0 cites
- 4832US6304939B1Token mechanism for cache-line replacement within a cache memory having redundant cache linesIBM·Filed 1999·Granted Oct 16, 2001·3 cites·11 claims
- 4931US7187614B2Array read access control using MUX select signal gating of the read portIBM·Filed 2004·Granted Mar 6, 2007·0 cites·20 claims
- 5030US6604173B1System for controlling access to external cache memories of differing sizeIBM·Filed 1995·Granted Aug 5, 2003·0 cites·10 claims
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