Inventor · disambiguated record
John A. Bracchitta
Also filed as: BRACCHITTA JOHN A · BRACCHITTA JOHN ANTHONY
25 granted patents·826 citations·filing 1995–2007
97Inventor score
Files withIBM25
Top patents by PatentIndex Score
25 records- 0198US6483156B1Double planar gated SOI MOSFET structureIBM·Filed 2000·Granted Nov 19, 2002·210 cites·7 claims
- 0296US7195971B2Method of manufacturing an intralevel decoupling capacitorIBM·Filed 2005·Granted Mar 27, 2007·26 cites·18 claims
- 0394US6882015B2Intralevel decoupling capacitor, method of manufacture and testing circuit of the sameIBM·Filed 2003·Granted Apr 19, 2005·49 cites·16 claims
- 0489US6660596B2Double planar gated SOI MOSFET structureIBM·Filed 2002·Granted Dec 9, 2003·46 cites·9 claims
- 0588US6677637B2Intralevel decoupling capacitor, method of manufacture and testing circuit of the sameIBM·Filed 1999·Granted Jan 13, 2004·66 cites·19 claims
- 0685US6100123APillar CMOS structureIBM·Filed 1998·Granted Aug 8, 2000·49 cites·13 claims
- 0783US6373095B1NVRAM cell having increased coupling ratio between a control gate and floating gate without an increase in cell areaIBM·Filed 1998·Granted Apr 16, 2002·56 cites·8 claims
- 0883US6130469AElectrically alterable antifuse using FETIBM·Filed 1998·Granted Oct 10, 2000·70 cites·5 claims
- 0980US7089192B2Intellectual property management method and apparatusIBM·Filed 2000·Granted Aug 8, 2006·28 cites·45 claims
- 1079US6261895B1Polysilicon capacitor having large capacitance and low resistance and process for forming the capacitorIBM·Filed 1999·Granted Jul 17, 2001·47 cites·16 claims
- 1177US6394638B1Trench isolation for active areas and first level conductorsIBM·Filed 2000·Granted May 28, 2002·19 cites·10 claims
- 1271US6020777AElectrically programmable anti-fuse circuitIBM·Filed 1997·Granted Feb 1, 2000·27 cites·13 claims
- 1370US6060358ADamascene NVRAM cell and method of manufactureIBM·Filed 1997·Granted May 9, 2000·30 cites·17 claims
- 1468US5734192ATrench isolation for active areas and first level conductorsIBM·Filed 1995·Granted Mar 31, 1998·29 cites·20 claims
- 1567US6255699B1Pillar CMOS structureIBM·Filed 2000·Granted Jul 3, 2001·10 cites·4 claims
- 1666US7630915B2Intellectual property management method and apparatusIBM·Filed 2006·Granted Dec 8, 2009·2 cites·6 claims
- 1765US5518945AMethod of making a diffused lightly doped drain device with built in etch stopIBM·Filed 1995·Granted May 21, 1996·37 cites·9 claims
- 1859US6339015B1Method of fabricating a non-volatile semiconductor deviceIBM·Filed 2000·Granted Jan 15, 2002·7 cites·15 claims
- 1956US7323382B2Intralevel decoupling capacitor, method of manufacture and testing circuit of the sameIBM·Filed 2007·Granted Jan 29, 2008·0 cites·14 claims
- 2056US5949265ASoft latch circuit having sharp-cornered hysteresis characteristicsIBM·Filed 1997·Granted Sep 7, 1999·13 cites·20 claims
- 2153US6858889B2Polysilicon capacitor having large capacitance and low resistanceIBM·Filed 2001·Granted Feb 22, 2005·3 cites·4 claims
- 2238US6344381B1Method for forming pillar CMOSIBM·Filed 2000·Granted Feb 5, 2002·0 cites·1 claims
- 2333US6232633B1NVRAM cell using sharp tip for tunnel eraseIBM·Filed 1998·Granted May 15, 2001·2 cites·6 claims
- 2430US6063687AFormation of trench isolation for active areas and first level conductorsIBM·Filed 1997·Granted May 16, 2000·0 cites·12 claims
- 2529US6420746B1Three device DRAM cell with integrated capacitor and local interconnectIBM·Filed 1998·Granted Jul 16, 2002·0 cites·16 claims
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