Inventor · disambiguated record
Gary K. Giust
Also filed as: GIUST GARY · GIUST GARY K
21 granted patents·2 pending applications·335 citations·filing 1997–2023
95Inventor score
Top patents by PatentIndex Score
23 records- 0193US6544854B1Silicon germanium CMOS channelLSI LOGIC CORP·Filed 2000·Granted Apr 8, 2003·70 cites·18 claims
- 0289US8891602B1Analyzing jitter with noise from the measurement environmentGIUST GARY K·Filed 2012·Granted Nov 18, 2014·13 cites·23 claims
- 0388US8473233B1Analyzing jitter in a clock timing signalGIUST GARY K·Filed 2010·Granted Jun 25, 2013·9 cites·68 claims
- 0486US10802074B2Method and apparatus for analyzing phase noise in a signal from an electronic deviceJITTERLABS LLC·Filed 2018·Granted Oct 13, 2020·2 cites·24 claims
- 0578US2023184828A1Method and Apparatus for Analyzing Phase Noise in a Signal from an Electronic DeviceJITTERLABS LLC·Filed 2023·Application pending·0 cites
- 0677US6455363B1System to improve ser immunity and punchthroughLSI LOGIC CORP·Filed 2000·Granted Sep 24, 2002·21 cites·16 claims
- 0775US11592480B2Method and apparatus for analyzing phase noise in a signal from an electronic deviceJITTERLABS LLC·Filed 2021·Granted Feb 28, 2023·0 cites·10 claims
- 0875US5953614AProcess for forming self-aligned metal silicide contacts for MOS structure using single silicide-forming stepLSI LOGIC CORP·Filed 1997·Granted Sep 14, 1999·48 cites·23 claims
- 0972US6977400B2Silicon germanium CMOS channelLSI LOGIC CORP·Filed 2003·Granted Dec 20, 2005·15 cites·1 claims
- 1072US6442061B1Single channel four transistor SRAMLSI LOGIC CORP·Filed 2001·Granted Aug 27, 2002·15 cites·12 claims
- 1171US11231459B2Method and apparatus for analyzing phase noise in a signal from an electronic deviceJITTERLABS LLC·Filed 2020·Granted Jan 25, 2022·0 cites·24 claims
- 1269US6566730B1Laser-breakable fuse link with alignment and break point promotion structuresLSI LOGIC CORP·Filed 2000·Granted May 20, 2003·15 cites·28 claims
- 1368US6218276B1Silicide encapsulation of polysilicon gate and interconnectLSI LOGIC CORP·Filed 1997·Granted Apr 17, 2001·28 cites·26 claims
- 1467US6413848B1Self-aligned fuse structure and method with dual-thickness dielectricLSI LOGIC CORP·Filed 2000·Granted Jul 2, 2002·14 cites·9 claims
- 1562US6259146B1Self-aligned fuse structure and method with heat sinkLSI LOGIC CORP·Filed 1998·Granted Jul 10, 2001·26 cites·22 claims
- 1660US6061264ASelf-aligned fuse structure and method with anti-reflective coatingLSI LOGIC CORP·Filed 1998·Granted May 9, 2000·18 cites·16 claims
- 1759US6037233AMetal-encapsulated polysilicon gate and interconnectLSI LOGIC CORP·Filed 1998·Granted Mar 14, 2000·18 cites·13 claims
- 1850US9003549B2Analysis of an analog property of a signalGIUST GARY K·Filed 2011·Granted Apr 7, 2015·0 cites·46 claims
- 1950US7388440B1Circuit and method to speed up PLL lock-time and prohibit frequency runawayCYPRESS SEMICONDUCTOR CORP·Filed 2004·Granted Jun 17, 2008·6 cites·3 claims
- 2045US6090651ADepletion free polysilicon gate electrodesLSI LOGIC CORP·Filed 1999·Granted Jul 18, 2000·9 cites·20 claims
- 2143US6770947B2Laser-breakable fuse link with alignment and break point promotion structuresLSI LOGIC CORP·Filed 2003·Granted Aug 3, 2004·1 cites·13 claims
- 2242US6162714AMethod of forming thin polygates for sub quarter micron CMOS processLSI LOGIC CORP·Filed 1997·Granted Dec 19, 2000·7 cites·8 claims
- 2339US2002173087A1System to improve SER immunity and punchthroughLSI LOGIC CORP·Filed 2002·Application pending·0 cites
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