Inventor · disambiguated record
Jens K. Ramsey
Also filed as: RAMSEY JENS K
17 granted patents·643 citations·filing 1992–2003
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
17 records- 0186US5325503ACache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same lineCOMPAQ COMPUTER CORP·Filed 1992·Granted Jun 28, 1994·107 cites·10 claims
- 0282US5426765AMultiprocessor cache abitrationCOMPAQ COMPUTER CORP·Filed 1994·Granted Jun 20, 1995·97 cites·16 claims
- 0375US6209067B1Computer system controller and method with processor write posting hold off on PCI master memory requestCOMPAQ COMPUTER CORP·Filed 1995·Granted Mar 27, 2001·75 cites·14 claims
- 0475US5634073ASystem having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operationCOMPAQ COMPUTER CORP·Filed 1994·Granted May 27, 1997·53 cites·2 claims
- 0573US5446863ACache snoop latency prevention apparatusCOMPAQ COMPUTER CORP·Filed 1993·Granted Aug 29, 1995·53 cites·3 claims
- 0671US5822571ASynchronizing data between devicesCOMPAQ COMPUTER CORP·Filed 1996·Granted Oct 13, 1998·60 cites·26 claims
- 0770US5813022ACircuit for placing a cache memory into low power mode in response to special bus cycles executed on the busCOMPAQ COMPUTER CORP·Filed 1996·Granted Sep 22, 1998·56 cites·9 claims
- 0857US5938739AMemory controller including write posting queues, bus read control logic, and a data contents counterCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 17, 1999·25 cites·26 claims
- 0956US6041401AComputer system that places a cache memory into low power mode in response to special bus cycles executed on the busCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 21, 2000·27 cites·5 claims
- 1055US7120758B2Technique for improving processor performanceHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Oct 10, 2006·4 cites·26 claims
- 1152US5640532AMicroprocessor cache memory way prediction based on the way of previous memory readCOMPAQ COMPUTER CORP·Filed 1994·Granted Jun 17, 1997·21 cites·5 claims
- 1246US5835948ASingle bank, multiple way cache memoryCOMPAQ COMPUTER CORP·Filed 1994·Granted Nov 10, 1998·16 cites·34 claims
- 1345US5872939ABus arbitrationCOMPAQ COMPUTER CORP·Filed 1996·Granted Feb 16, 1999·16 cites·38 claims
- 1444US5895490AComputer system cache performance on write allocation cycles by immediately setting the modified bit trueCOMPAQ COMPUTER CORP·Filed 1997·Granted Apr 20, 1999·14 cites·26 claims
- 1539US5822756AMicroprocessor cache memory way prediction based on the way of a previous memory readCOMPAQ COMPUTER CORP·Filed 1997·Granted Oct 13, 1998·10 cites·33 claims
- 1636US5781925AMethod of preventing cache corruption during microprocessor pipelined burst operationsCOMPAQ COMPUTER CORP·Filed 1995·Granted Jul 14, 1998·8 cites·22 claims
- 1730US5699550AComputer system cache performance on write allocation cycles by immediately setting the modified bit trueCOMPAQ COMPUTER CORP·Filed 1994·Granted Dec 16, 1997·1 cites·8 claims
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