Inventor · disambiguated record
Terutoshi Yamasaki
Also filed as: YAMASAKI TERUTOSHI
3 granted patents·1 pending application·25 citations·filing 1996–2003
68Inventor score
Technology areasG06F
Top patents by PatentIndex Score
4 records- 0141US6965853B2Back annotation apparatus for carrying out a simulation based on the extraction result in regard to parasitic elementsRENESAS TECH CORP·Filed 2001·Granted Nov 15, 2005·3 cites·10 claims
- 0241US2004049747A1Verification apparatusRENESAS TECH CORP·Filed 2003·Application pending·0 cites
- 0336US5699264ASemiconductor circuit design verifying apparatusMITSUBISHI ELEC SEMICONDUCTOR·Filed 1996·Granted Dec 16, 1997·11 cites·11 claims
- 0433US6427225B1Method and apparatus for verification of a circuit layoutMITSUBISHI ELECTRIC CORP·Filed 1999·Granted Jul 30, 2002·11 cites·12 claims
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