Inventor · disambiguated record
Mark A. Horowitz
Also filed as: HOROWITZ MARK · HOROWITZ MARK A · HOROWITZ MARK ALAN
247 granted patents·11 pending applications·15,192 citations·filing 1992–2024
99Inventor score
Files withRAMBUS INC204UNIV LELAND STANFORD JUNIOR21NG YI-REN5STOJANOVIC VLADIMIR M5HOROWITZ MARK A3
Top patents by PatentIndex Score
258 records- 0199US8199859B2Integrating receiver with precharge circuitryZERBE JARED L·Filed 2010·Granted Jun 12, 2012·142 cites·31 claims
- 0299US7936392B2Imaging arrangements and methods thereforUNIV LELAND STANFORD JUNIOR·Filed 2005·Granted May 3, 2011·165 cites·14 claims
- 0399US7723662B2Microscopy arrangements and approachesUNIV LELAND STANFORD JUNIOR·Filed 2006·Granted May 25, 2010·316 cites·24 claims
- 0499US7456778B2Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signalsRAMBUS INC·Filed 2006·Granted Nov 25, 2008·80 cites·24 claims
- 0599US6643787B1Bus system optimizationRAMBUS INC·Filed 1999·Granted Nov 4, 2003·424 cites·6 claims
- 0699US6584037B2Memory device which samples data after an amount of time transpiresRAMBUS INC·Filed 2002·Granted Jun 24, 2003·135 cites·45 claims
- 0799US6539072B1Delay locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 2000·Granted Mar 25, 2003·263 cites·31 claims
- 0899US6321282B1Apparatus and method for topography dependent signalingRAMBUS INC·Filed 1999·Granted Nov 20, 2001·360 cites·50 claims
- 0999US6185644B1Memory system including a plurality of memory devices and a transceiver deviceRAMBUS INC·Filed 2000·Granted Feb 6, 2001·228 cites·22 claims
- 1099US6125157ADelay-locked loop circuitry for clock delay adjustmentRAMBUS INC·Filed 1997·Granted Sep 26, 2000·382 cites·20 claims
- 1199US5928343AMemory module having memory devices containing internal device ID registers and method of initializing sameRAMBUS INC·Filed 1998·Granted Jul 27, 1999·343 cites·29 claims
- 1299US5638334AIntegrated circuit I/O using a high performance bus interfaceRAMBUS INC·Filed 1995·Granted Jun 10, 1997·258 cites·13 claims
- 1399US5606717AMemory circuitry having bus interface for receiving information in packets and access time registersRAMBUS INC·Filed 1992·Granted Feb 25, 1997·441 cites·6 claims
- 1499US5513327AIntegrated circuit I/O using a high performance bus interfaceRAMBUS INC·Filed 1994·Granted Apr 30, 1996·271 cites·29 claims
- 1599US5319755AIntegrated circuit I/O using high performance bus interfaceRAMBUS INC·Filed 1992·Granted Jun 7, 1994·472 cites·59 claims
- 1699US5243703AApparatus for synchronously generating clock signals in a data processing systemRAMBUS INC·Filed 1992·Granted Sep 7, 1993·570 cites·13 claims
- 1798US8344475B2Integrated circuit heating to effect in-situ annealingRAMBUS INC·Filed 2010·Granted Jan 1, 2013·50 cites·38 claims
- 1898US7831882B2Memory system with error detection and retry modes of operationRAMBUS INC·Filed 2005·Granted Nov 9, 2010·59 cites·13 claims
- 1998US6950956B2Integrated circuit with timing adjustment mechanism and methodRAMBUS INC·Filed 2003·Granted Sep 27, 2005·169 cites·21 claims
- 2098US6772351B1Method and apparatus for calibrating a multi-level current mode driverRAMBUS INC·Filed 2000·Granted Aug 3, 2004·139 cites·21 claims
- 2198US6697295B2Memory device having a programmable registerRAMBUS INC·Filed 2001·Granted Feb 24, 2004·106 cites·51 claims
- 2298US6684263B2Apparatus and method for topography dependent signalingRAMBUS INC·Filed 2003·Granted Jan 27, 2004·127 cites·52 claims
- 2398US6516365B2Apparatus and method for topography dependent signalingRAMBUS INC·Filed 2001·Granted Feb 4, 2003·148 cites·32 claims
- 2498US6378020B2System having double data transfer rate and intergrated circuit thereforRAMBUS INC·Filed 2000·Granted Apr 23, 2002·95 cites·41 claims
- 2598US6314051B1Memory device having write latencyRAMBUS INC·Filed 2000·Granted Nov 6, 2001·149 cites·43 claims
- 2698US6266285B1Method of operating a memory device having write latencyRAMBUS INC·Filed 2000·Granted Jul 24, 2001·146 cites·33 claims
- 2798US6260097B1Method and apparatus for controlling a synchronous memory deviceRAMBUS INC·Filed 2000·Granted Jul 10, 2001·135 cites·35 claims
- 2898US6182184B1Method of operating a memory device having a variable data input lengthRAMBUS INC·Filed 2000·Granted Jan 30, 2001·116 cites·29 claims
- 2998US6038195ASynchronous memory device having a delay time register and method of operating sameRAMBUS INC·Filed 1998·Granted Mar 14, 2000·147 cites·40 claims
- 3098US6035365ADual clocked synchronous memory device having a delay time register and method of operating sameRAMBUS INC·Filed 1998·Granted Mar 7, 2000·134 cites·52 claims
- 3198US6032215ASynchronous memory device utilizing two external clocksRAMBUS INC·Filed 1999·Granted Feb 29, 2000·107 cites·38 claims
- 3298US6032214AMethod of operating a synchronous memory device having a variable data output lengthRAMBUS INC·Filed 1999·Granted Feb 29, 2000·160 cites·37 claims
- 3398US5841580AIntegrated circuit I/O using a high performance bus interfaceRAMBUS INC·Filed 1997·Granted Nov 24, 1998·115 cites·22 claims
- 3498US5657481AMemory device with a phase locked loop circuitryRAMBUS INC·Filed 1996·Granted Aug 12, 1997·161 cites·18 claims
- 3598US5485490AMethod and circuitry for clock synchronizationRAMBUS INC·Filed 1994·Granted Jan 16, 1996·433 cites·24 claims
- 3698US5473575AIntegrated circuit I/O using a high performance bus interfaceRAMBUS INC·Filed 1992·Granted Dec 5, 1995·117 cites·6 claims
- 3798US5254883AElectrical current source circuitry for a busRAMBUS INC·Filed 1992·Granted Oct 19, 1993·537 cites·39 claims
- 3897US8248515B2Variable imaging arrangements and methods thereforNG YI-REN·Filed 2007·Granted Aug 21, 2012·56 cites·24 claims
- 3997US8027531B2Apparatus and method for capturing a scene using staggered triggering of dense camera arraysUNIV LELAND STANFORD JUNIOR·Filed 2005·Granted Sep 27, 2011·243 cites·20 claims
- 4097US7715509B2Partial response receiverRAMBUS INC·Filed 2009·Granted May 11, 2010·31 cites·49 claims
- 4197US7535933B2Calibrated data communication system and methodRAMBUS INC·Filed 2006·Granted May 19, 2009·58 cites·17 claims
- 4297US7210015B2Memory device having at least a first and a second operating modeRAMBUS INC·Filed 2005·Granted Apr 24, 2007·37 cites·24 claims
- 4397US7174400B2Integrated circuit device that stores a value representative of an equalization co-efficient settingRAMBUS INC·Filed 2005·Granted Feb 6, 2007·34 cites·33 claims
- 4497US7142612B2Method and apparatus for multi-level signalingRAMBUS INC·Filed 2001·Granted Nov 28, 2006·193 cites·48 claims
- 4597US7110322B2Memory module including an integrated circuit deviceRAMBUS INC·Filed 2004·Granted Sep 19, 2006·67 cites·31 claims
- 4697US7042914B2Calibrated data communication system and methodRAMBUS INC·Filed 2003·Granted May 9, 2006·93 cites·17 claims
- 4797US6751696B2Memory device having a programmable registerRAMBUS INC·Filed 2001·Granted Jun 15, 2004·106 cites·60 claims
- 4897US6564281B2Synchronous memory device having automatic prechargeRAMBUS INC·Filed 2001·Granted May 13, 2003·75 cites·46 claims
- 4997US6546446B2Synchronous memory device having automatic prechargeRAMBUS INC·Filed 2001·Granted Apr 8, 2003·73 cites·45 claims
- 5097US6452863B2Method of operating a memory device having a variable data input lengthRAMBUS INC·Filed 2000·Granted Sep 17, 2002·74 cites·35 claims
Showing the top 50 of 258 patent records by PatentIndex Score.
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