Inventor · disambiguated record
Liang-Jih Chao
Also filed as: CHAO LIANG-JIH
7 granted patents·1 pending application·130 citations·filing 1999–2013
86Inventor score
Technology areasG06F
Top patents by PatentIndex Score
8 records- 0190US7036101B2Method and apparatus for scalable interconnect solutionCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Apr 25, 2006·54 cites·42 claims
- 0274US9177093B2Routing interconnect of integrated circuit designs with varying grid densitiesCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Nov 3, 2015·4 cites·12 claims
- 0370US8386984B2Interconnect routing methods of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Feb 26, 2013·3 cites·11 claims
- 0468US8255857B2Routing methods for integrated circuit designsHE LIMIN·Filed 2008·Granted Aug 28, 2012·3 cites·13 claims
- 0566US8365128B2Routing interconnect of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Jan 29, 2013·2 cites·24 claims
- 0664US6367060B1Method and apparatus for clock tree solution synthesis based on design constraintsFiled 1999·Granted Apr 2, 2002·62 cites·20 claims
- 0763US8291365B2Conditionally routing a portion of an integrated circuit design with a different pitch to overcome a design rule violationHE LIMIN·Filed 2006·Granted Oct 16, 2012·2 cites·29 claims
- 0850US2013031524A1Routing methods for integrated circuit designsHE LIMIN·Filed 2012·Application pending·0 cites
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