Inventor · disambiguated record
Chih-Jui Peng
Also filed as: PENG CHIH-JUI · PENG CHIH-JUI RAY
13 granted patents·2 pending applications·219 citations·filing 1994–1999
93Inventor score
Technology areasG06F
Top patents by PatentIndex Score
15 records- 0154US5682495AFully associative address translation buffer having separate segment and page invalidationIBM·Filed 1994·Granted Oct 28, 1997·28 cites·6 claims
- 0252US5604879ASingle array address translator with segment and page invalidate ability and method of operationMOTOROLA INC·Filed 1996·Granted Feb 18, 1997·33 cites·4 claims
- 0352US5535351AAddress translator with by-pass circuit and method of operationMOTOROLA INC·Filed 1994·Granted Jul 9, 1996·24 cites·8 claims
- 0448US6633971B2Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipelineHITACHI LTD·Filed 1999·Granted Oct 14, 2003·20 cites·24 claims
- 0547US5530822AAddress translator and method of operationMOTOROLA INC·Filed 1994·Granted Jun 25, 1996·20 cites·10 claims
- 0646US5974535AMethod and system in data processing system of permitting concurrent processing of instructions of a particular typeIBM·Filed 1997·Granted Oct 26, 1999·19 cites·13 claims
- 0745US6449712B1Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructionsHITACHI LTD·Filed 1999·Granted Sep 10, 2002·18 cites·3 claims
- 0841US6408381B1Mechanism for fast access to control space in a pipeline processorHITACHI LTD·Filed 1999·Granted Jun 18, 2002·15 cites·7 claims
- 0938US6477638B1Synchronized instruction advancement through CPU and FPU pipelinesHITACHI LTD·Filed 1999·Granted Nov 5, 2002·12 cites·9 claims
- 1038US6393523B1Mechanism for invalidating instruction cache blocks in a pipeline processorHITACHI LTD·Filed 1999·Granted May 21, 2002·11 cites·14 claims
- 1135US6542983B1Microcomputer/floating point processor interface and methodHITACHI LTD·Filed 1999·Granted Apr 1, 2003·8 cites·3 claims
- 1233US6457118B1Method and system for selecting and using source operands in computer system instructionsHITACHI LTD·Filed 1999·Granted Sep 24, 2002·5 cites·16 claims
- 1333US6351803B2Mechanism for power efficient processing in a pipeline processorHITACHI LTD·Filed 1999·Granted Feb 26, 2002·6 cites·14 claims
- 1427US2002161985A1Microcomputer/floating point processor interface and method for synchronization of cpu and fpu pipelinesFiled 1999·Application pending·0 cites
- 1527US2002056034A1Mechanism and method for pipeline control in a processorFiled 1999·Application pending·0 cites
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