Inventor

MURALIMANOHAR NAVEEN

US65 patents

⚠️ This page may combine multiple inventors who share the name “MURALIMANOHAR NAVEEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MURALIMANOHAR NAVEEN

HEWLETT PACKARD ENTPR DEV LP

Vector-matrix multiplications involving negative values

Data processing using resistive memory arrays

Matrix circuits

Memory access methods and apparatus

Analog sub-matrix computing from input matrixes

Circuits having selector devices with different I-V responses

Dot product engine with negation indicator

Draining a write queue based on information from a read queue

Management controller

Hierarchical computations on sparse matrix rows via a memristor array

Reusing sneak current in accessing memory cells

Convolution accelerators

Smart memory buffers

Determining a resistance state of a cell in a crossbar memory array

Memristive dot product circuit based floating point computations

Proactive cluster compute node migration at next checkpoint of cluster upon predicted node failure

Processing in-memory architectures for performing logical operations

Proactive cluster compute node migration at next checkpoint of cluster cluster upon predicted node failure

Retrieve data block from determined devices

Smart memory buffers

Data write to subset of memory devices

Encoding data within a crossbar memory array

Floating point data set compression

Identifying outlying values in matrices

Signal conversion using an analog-to-digital converter and reference voltage comparison

Non-volatile memory with multiple latency tiers

Versioned memory Implementation

MURALIMANOHAR NAVEEN

Memory access methods and apparatus

Interface methods and apparatus for memory devices using arbitration

Random-access memory with dynamically adjustable endurance and retention

Parallelized check pointing using MATs and through silicon VIAs (TSVs)

Multi-level cell memory

Checkpointing in massively parallel processing

Controlling nanostore operation based on monitored performance

HEWLETT PACKARD DEVELOPMENT CO LP

Adaptive granularity row-buffer cache

Non-volatile multi-level-cell memory with decoupled bits for higher performance and energy efficiency

Radix enhancement for photonic packet switch

Representing data using a group of multilevel memory cells

HEWLETT PACKARD DEVELOPMENT CO

Memory error identification based on corrupted symbol patterns

Global error correction

Invoking an error handler to handle an uncorrectable error

AMAZON TECH INC

Caching results for sub-queries to different data store locations

Sharing compiled code for executing queries across query engines

LI SHENG

Managing chip multi-processors through virtual domains

Methods and apparatus to perform error detection and correction

FARABOSCHI PAOLO

Securing non-volatile memory regions

UDIPI ANIRUDDHA NAGENDRAN

Local error detection and global error correction

MOGUL JEFFREY CLIFFORD

Methods and apparatus to access memory using runtime characteristics

YOON DOE HYUN

Computing system reliability

UNIV UTAH TECHNOLOGY COMMERCIA

Microarchitectural wire management for performance and power in partitioned architectures