Inventor · disambiguated record
Alfred T. Watson, Iii
Also filed as: WATSON ALFRED T · WATSON ALFRED T III · WATSON ALFRED THOMAS · WATSON III ALFRED T
14 granted patents·5 pending applications·248 citations·filing 2004–2018
92Inventor score
Top patents by PatentIndex Score
19 records- 0196US9971713B2Multi-petascale highly efficient parallel supercomputerGLOBALFOUNDRIES INC·Filed 2015·Granted May 15, 2018·30 cites·14 claims
- 0296US9081501B2Multi-petascale highly efficient parallel supercomputerASAAD SAMEH·Filed 2011·Granted Jul 14, 2015·115 cites·41 claims
- 0392US7917703B2Network on chip that maintains cache coherency with invalidate commandsIBM·Filed 2007·Granted Mar 29, 2011·29 cites·16 claims
- 0491US9354884B2Processor with hybrid pipeline capable of operating in out-of-order and in-order modesIBM·Filed 2013·Granted May 31, 2016·12 cites·22 claims
- 0591US8082420B2Method and apparatus for executing instructionsCOMPARAN MIGUEL·Filed 2007·Granted Dec 20, 2011·38 cites·14 claims
- 0685US8856602B2Multi-core processor with internal voting-based built in self test (BIST)BROWN JEFFREY D·Filed 2011·Granted Oct 7, 2014·9 cites·25 claims
- 0784US10114652B2Processor with hybrid pipeline capable of operating in out-of-order and in-order modesIBM·Filed 2016·Granted Oct 30, 2018·3 cites·18 claims
- 0881US9092347B2Allocating cache for use as a dedicated local storageIBM·Filed 2012·Granted Jul 28, 2015·5 cites·16 claims
- 0972US9021237B2Low latency variable transfer network communicating variable written to source processing core variable register allocated to destination thread to destination processing core variable register allocated to source threadCOMPARAN MIGUEL·Filed 2011·Granted Apr 28, 2015·3 cites·23 claims
- 1069US8949836B2Transferring architected state between coresCOMPARAN MIGUEL·Filed 2011·Granted Feb 3, 2015·2 cites·13 claims
- 1164US9053037B2Allocating cache for use as a dedicated local storageCOMPARAN MIGUEL·Filed 2011·Granted Jun 9, 2015·1 cites·13 claims
- 1262US8560924B2Register file soft error recoveryFLEISCHER BRUCE M·Filed 2010·Granted Oct 15, 2013·1 cites·18 claims
- 1361US10831504B2Processor with hybrid pipeline capable of operating in out-of-order and in-order modesIBM·Filed 2018·Granted Nov 10, 2020·0 cites·17 claims
- 1453US8954973B2Transferring architected state between coresIBM·Filed 2012·Granted Feb 10, 2015·0 cites·7 claims
- 1547US2006045031A1Automatic hardware data link initialization using multiple state machinesIBM·Filed 2004·Application pending·0 cites
- 1643US2007073933A1Asynchronous interface with vectored interface controlsIBM·Filed 2005·Application pending·0 cites
- 1743US2009284524A1Optimized Graphical Calculation Performance by Removing Divide RequirementsSHEARER ROBERT ALLEN·Filed 2008·Application pending·0 cites
- 1841US2006159023A1CRC error history mechanismIBM·Filed 2005·Application pending·0 cites
- 1941US2008088619A1Branch Prediction for Acceleration Data Structure TraversalSHEARER ROBERT ALLEN·Filed 2006·Application pending·0 cites
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