Inventor · disambiguated record
Adam B. Healey
Also filed as: HEALEY ADAM · HEALEY ADAM B · HEALEY ADAM BENJAMIN
26 granted patents·4 pending applications·159 citations·filing 2002–2025
95Inventor score
Top patents by PatentIndex Score
30 records- 0196US9077574B1DSP SerDes receiver with FFE-DFE-DFFE data pathLSI CORP·Filed 2014·Granted Jul 7, 2015·48 cites·17 claims
- 0291US8860467B2Biased bang-bang phase detector for clock and data recoveryLSI CORP·Filed 2013·Granted Oct 14, 2014·12 cites·11 claims
- 0390US11689395B2Efficient architecture for high-performance DSP-based SERDESAVAGO TECH INT SALES PTE LID·Filed 2021·Granted Jun 27, 2023·2 cites·20 claims
- 0488US9130797B1Pipelined decision feedback equalization in an interleaved serializer/deserializer receiverLSI CORP·Filed 2014·Granted Sep 8, 2015·11 cites·20 claims
- 0586US2025357917A1Efficient architecture for high-performance dsp-based long-reach serdesAVAGO TECH INT SALES PTE LID·Filed 2025·Application pending·0 cites
- 0685US8976854B1Method and apparatus for feed forward equalizer with variable cursor positionLSI CORP·Filed 2014·Granted Mar 10, 2015·8 cites·15 claims
- 0783US10511549B2High-speed interconnect solutions with support for continuous time in-band back channel communication and proprietary featuresAVAGO TECH INT SALES PTE LID·Filed 2017·Granted Dec 17, 2019·4 cites·20 claims
- 0882US8467440B2Compensated phase detector for generating one or more clock signals using DFE detected data in a receiverAZIZ PERVEZ M·Filed 2010·Granted Jun 18, 2013·7 cites·13 claims
- 0981US8787439B2Decision feedforward equalizationPALUSA CHAITANYA·Filed 2012·Granted Jul 22, 2014·9 cites·17 claims
- 1080US8279950B2Compensation for transmission line length variation in a SERDES systemAZIZ PERVEZ M·Filed 2011·Granted Oct 2, 2012·5 cites·20 claims
- 1179US12401346B2Efficient architecture for high-performance DSP-based long-reach SERDESAVAGO TECH INT SALES PTE LID·Filed 2023·Granted Aug 26, 2025·0 cites·20 claims
- 1278US10715356B2High-speed interconnect solutions with support for secondary continuous time in-band back channel communication for simplex retimer solutionsAVAGO TECH INT SALES PTE LID·Filed 2017·Granted Jul 14, 2020·3 cites·17 claims
- 1378US9215106B2Method and apparatus for pre-cursor intersymbol interference correctionLSI CORP·Filed 2014·Granted Dec 15, 2015·6 cites·20 claims
- 1476US10530906B2High-speed interconnect solutions with support for continuous time back channel communicationAVAGO TECH INT SALES PTE LID·Filed 2017·Granted Jan 7, 2020·2 cites·20 claims
- 1576US8379711B2Methods and apparatus for decision-feedback equalization with oversampled phase detectorLSI CORP·Filed 2009·Granted Feb 19, 2013·6 cites·22 claims
- 1676US8054892B2Compensating transmission line to reduce sensitivity of performance due to channel length variationAGERE SYSTEMS INC·Filed 2009·Granted Nov 8, 2011·5 cites·20 claims
- 1772US9036729B2Code forwarding and clock generation for transmitter repeatersLSI CORP·Filed 2013·Granted May 19, 2015·3 cites·17 claims
- 1864US7593327B2Method and apparatus for frequency offset control of ethernet packets over a transport networkAGERE SYSTEMS INC·Filed 2003·Granted Sep 22, 2009·13 cites·20 claims
- 1962US8040984B2Methods and apparatus for improved jitter tolerance in an SFP limit amplified signalAGERE SYSTEM INC·Filed 2007·Granted Oct 18, 2011·2 cites·20 claims
- 2062US7353245B2Adaptive filter coefficient determinationAGERE SYSTEMS INC·Filed 2002·Granted Apr 1, 2008·9 cites·23 claims
- 2160US8687682B2Transmitter adaptation loop using adjustable gain and convergence detectionMOBIN MOHAMMAD·Filed 2012·Granted Apr 1, 2014·1 cites·48 claims
- 2256US8085837B2Characterizing non-compensable jitter in an electronic signalHEALEY ADAM B·Filed 2008·Granted Dec 27, 2011·2 cites·22 claims
- 2354US7813285B2Method for per-port flow control of packets aggregated from multiple logical ports over a transport linkAGERE SYSTEMS INC·Filed 2008·Granted Oct 12, 2010·1 cites·19 claims
- 2452US10560555B2High-speed interconnect solutions with support for co-propagating and counter-propagating continuous time back channel communicationAVAGO TECH INT SALES PTE LID·Filed 2017·Granted Feb 11, 2020·0 cites·21 claims
- 2552US9304535B2Baud rate phase detector with no error latchesLSI CORP·Filed 2014·Granted Apr 5, 2016·0 cites·20 claims
- 2649US8902959B2System and method for determining channel loss in a dispersive communication channel at the Nyquist frequencyLSI CORP·Filed 2013·Granted Dec 2, 2014·0 cites·20 claims
- 2747US9385893B2Modular low power serializer-deserializerLSI CORP·Filed 2014·Granted Jul 5, 2016·0 cites·18 claims
- 2844US2015256363A1Integrated PAM4/NRZ N-Way Parallel Digital Unrolled Decision Feedback Equalizer (DFE)LSI CORP·Filed 2014·Application pending·0 cites
- 2939US2019020511A1High-speed interconnect solutions with support for continuous time in-band back channel communication and proprietary communication speedsAVAGO TECHNOLOGIES GENERAL IP·Filed 2017·Application pending·0 cites
- 3038US2004085904A1Method for flow control of packets aggregated from multiple logical ports over a transport linkFiled 2002·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →