Inventor · disambiguated record
Sajitha Wijesuriya
Also filed as: WIJESURIYA SAJITHA · WIJESURIYA SAJITHA S
10 granted patents·1 pending application·225 citations·filing 1998–2009
89Inventor score
Top patents by PatentIndex Score
11 records- 0196US7385417B1Dual slice architectures for programmable logic devicesLATTICE SEMICONDUCTOR CORP·Filed 2006·Granted Jun 10, 2008·48 cites·31 claims
- 0295US6202182B1Method and apparatus for testing field programmable gate arraysLUCENT TECHNOLOGIES INC·Filed 1998·Granted Mar 13, 2001·147 cites·21 claims
- 0380US7592834B1Logic block control architectures for programmable logic devicesLATTICE SEMICONDUCTOR CORP·Filed 2008·Granted Sep 22, 2009·7 cites·16 claims
- 0476US7196963B1Address isolation for user-defined configuration memory in programmable devicesLATTICE SEMICONDUCTOR CORP·Filed 2005·Granted Mar 27, 2007·10 cites·19 claims
- 0565US7397276B1Logic block control architectures for programmable logic devicesLATTICE SEMICONDUCTOR CORP·Filed 2006·Granted Jul 8, 2008·3 cites·23 claims
- 0665US7183798B1Synchronous memoryLATTICE SEMICONDUCTOR CORP·Filed 2005·Granted Feb 27, 2007·5 cites·20 claims
- 0760US7675321B1Dual-slice architectures for programmable logic devicesLATTICE SEMICONDUCTOR CORP·Filed 2009·Granted Mar 9, 2010·2 cites·18 claims
- 0854US7696784B1Programmable logic device with multiple slice typesLATTICE SEMICONDUCTOR CORP·Filed 2008·Granted Apr 13, 2010·1 cites·6 claims
- 0953US7605606B1Area efficient routing architectures for programmable logic devicesLATTICE SEMICONDUCTOR CORP·Filed 2006·Granted Oct 20, 2009·2 cites·20 claims
- 1039US7378872B1Programmable logic device architecture with multiple slice typesLATTICE SEMICONDUCTOR CORP·Filed 2006·Granted May 27, 2008·0 cites·17 claims
- 1132US2005093577A1Multiplexer circuitsFiled 2003·Application pending·0 cites
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