Inventor · disambiguated record
Kiran Kumar Gullapalli
Also filed as: GULLAPALLI KIRAN · GULLAPALLI KIRAN K · GULLAPALLI KIRAN KUMAR
10 granted patents·100 citations·filing 1993–2014
88Inventor score
Files withMOTOROLA INC3FREESCALE SEMICONDUCTOR INC2GULLAPALLI KIRAN KUMAR2GULLAPALLI KIRAN1KERNS KEVIN J1
Top patents by PatentIndex Score
10 records- 0176US8886508B2Circuit simulation acceleration using model cachingGULLAPALLI KIRAN KUMAR·Filed 2011·Granted Nov 11, 2014·7 cites·19 claims
- 0275US9135383B2Table model circuit simulation acceleration using model cachingGULLAPALLI KIRAN·Filed 2012·Granted Sep 15, 2015·7 cites·20 claims
- 0370US6536026B2Method and apparatus for analyzing small signal response and noise in nonlinear circuitsMOTOROLA INC·Filed 2001·Granted Mar 18, 2003·17 cites·20 claims
- 0461US5687355AApparatus and method for modeling a graded channel transistorMOTOROLA INC·Filed 1995·Granted Nov 11, 1997·43 cites·43 claims
- 0559US8060355B2Automatic, hierarchy-independent partitioning method for transistor-level circuit simulationKERNS KEVIN J·Filed 2007·Granted Nov 15, 2011·5 cites·7 claims
- 0658US9449129B2Method and apparatus for accelerating sparse matrix operations in full accuracy circuit simulationFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Sep 20, 2016·1 cites·11 claims
- 0753US7007253B2Method and apparatus for distortion analysis in nonlinear circuitsFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Feb 28, 2006·10 cites·23 claims
- 0843US10229234B2Method and apparatus to facilitate simulating a circuit connected to a multiport interconnect structureGULLAPALLI KIRAN KUMAR·Filed 2014·Granted Mar 12, 2019·0 cites·20 claims
- 0931US5408107ASemiconductor device apparatus having multiple current-voltage curves and zero-bias memoryUNIV TEXAS·Filed 1993·Granted Apr 18, 1995·2 cites·20 claims
- 1028US5799172AMethod of simulating an integrated circuitMOTOROLA INC·Filed 1996·Granted Aug 25, 1998·8 cites·20 claims
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