Inventor · disambiguated record
Joe Salmon
Also filed as: SALMON JOE · SALMON JOE H
15 granted patents·203 citations·filing 1999–2012
92Inventor score
Top patents by PatentIndex Score
15 records- 0194US6662305B1Fast re-synchronization of independent domain clocks after powerdown to enable fast system start-upINTEL CORP·Filed 1999·Granted Dec 9, 2003·110 cites·27 claims
- 0292US7459938B2Method and apparatus for power efficient and scalable memory interfaceINTEL CORP·Filed 2006·Granted Dec 2, 2008·26 cites·5 claims
- 0389US7401246B2Nibble de-skew method, apparatus, and systemINTEL CORP·Filed 2005·Granted Jul 15, 2008·19 cites·17 claims
- 0480US8495330B2Method and apparatus for interfacing with heterogeneous dual in-line memory modulesVERGIS GEORGE·Filed 2010·Granted Jul 23, 2013·6 cites·24 claims
- 0569US7447929B2Countering power resonanceINTEL CORP·Filed 2005·Granted Nov 4, 2008·8 cites·21 claims
- 0667US7555670B2Clocking architecture using a bidirectional clock portINTEL CORP·Filed 2005·Granted Jun 30, 2009·4 cites·18 claims
- 0762US7751274B2Extended synchronized clockINTEL CORP·Filed 2006·Granted Jul 6, 2010·2 cites·18 claims
- 0862US7324403B2Latency normalization by balancing early and late clocksINTEL CORP·Filed 2004·Granted Jan 29, 2008·8 cites·30 claims
- 0957US7243176B2Method and apparatus for power efficient and scalable memory interfaceINTEL CORP·Filed 2004·Granted Jul 10, 2007·7 cites·28 claims
- 1056US8468433B2Optimizing the size of memory devices used for error correction code storageBAINS KULJIT S·Filed 2012·Granted Jun 18, 2013·1 cites·20 claims
- 1156US8458507B2Bus frequency adjustment circuitry for use in a dynamic random access memory deviceSALMON JOE·Filed 2008·Granted Jun 4, 2013·2 cites·20 claims
- 1255US7307900B2Method and apparatus for optimizing strobe to clock relationshipINTEL CORP·Filed 2004·Granted Dec 11, 2007·8 cites·12 claims
- 1353US7954001B2Nibble de-skew method, apparatus, and systemINTEL CORP·Filed 2008·Granted May 31, 2011·0 cites·20 claims
- 1449US9237000B2Transceiver clock architecture with transmit PLL and receive slave delay linesMARTIN AARON·Filed 2006·Granted Jan 12, 2016·1 cites·14 claims
- 1548US8108761B2Optimizing the size of memory devices used for error correction code storageBAINS KULJIT S·Filed 2007·Granted Jan 31, 2012·1 cites·20 claims
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