Inventor · disambiguated record
Robert Steven Glanville
Also filed as: GLANVILLE ROBERT S · GLANVILLE ROBERT STEVEN
24 granted patents·1 pending application·717 citations·filing 2001–2012
97Inventor score
Top patents by PatentIndex Score
25 records- 0196US8321849B2Virtual architecture and instruction set for parallel thread computingNICKOLLS JOHN R·Filed 2007·Granted Nov 27, 2012·88 cites·23 claims
- 0295US8381203B1Insertion of multithreaded execution synchronization points in a software programNVIDIA CORP·Filed 2006·Granted Feb 19, 2013·55 cites·10 claims
- 0395US7006101B1Graphics API with branching capabilitiesNVIDIA CORP·Filed 2002·Granted Feb 28, 2006·117 cites·44 claims
- 0494US7002588B1System, method and computer program product for branching during programmable vertex processingNVIDIA CORP·Filed 2003·Granted Feb 21, 2006·76 cites·21 claims
- 0592US7681187B2Method and apparatus for register allocation in presence of hardware constraintsNVIDIA CORP·Filed 2005·Granted Mar 16, 2010·47 cites·19 claims
- 0692US6894687B1System, method and computer program product for vertex attribute aliasing in a graphics pipelineNVIDIA CORP·Filed 2001·Granted May 17, 2005·73 cites·7 claims
- 0791US8171461B1Primitive program compilation for flat attributes with provoking vertex independenceKILGARD MARK J·Filed 2006·Granted May 1, 2012·29 cites·20 claims
- 0889US9952977B2Cache operations and policies for a multi-threaded clientHEINRICH STEVEN JAMES·Filed 2010·Granted Apr 24, 2018·21 cites·25 claims
- 0989US7162716B2Software emulator for optimizing application-programmable vertex processingNVIDIA CORP·Filed 2001·Granted Jan 9, 2007·57 cites·18 claims
- 1088US8006236B1System and method for compiling high-level primitive programs into primitive program micro-codeNVIDIA CORP·Filed 2006·Granted Aug 23, 2011·20 cites·16 claims
- 1184US6844880B1System, method and computer program product for an improved programmable vertex processing model with instruction setNVIDIA CORP·Filed 2001·Granted Jan 18, 2005·29 cites·51 claims
- 1283US7268785B1System and method for interfacing graphics program modulesNVIDIA CORP·Filed 2002·Granted Sep 11, 2007·32 cites·99 claims
- 1383US6697064B1System, method and computer program product for matrix tracking during vertex processing in a graphics pipelineNVIDIA CORP·Filed 2001·Granted Feb 24, 2004·28 cites·28 claims
- 1482US8615646B2Unanimous branch instructions in a parallel thread processorNICKOLLS JOHN R·Filed 2010·Granted Dec 24, 2013·6 cites·21 claims
- 1579US7825933B1Managing primitive program vertex attributes as per-attribute arraysNVIDIA CORP·Filed 2006·Granted Nov 2, 2010·9 cites·18 claims
- 1676US8271763B2Unified addressing and instructions for accessing parallel memory spacesNICKOLLS JOHN R·Filed 2009·Granted Sep 18, 2012·7 cites·20 claims
- 1775US10360039B2Predicted instruction execution in parallel processors with reduced per-thread state information including choosing a minimum or maximum of two operands based on a predicate valueJOHNSON RICHARD CRAIG·Filed 2010·Granted Jul 23, 2019·5 cites·16 claims
- 1874US8677106B2Unanimous branch instructions in a parallel thread processorNICKOLLS JOHN R·Filed 2010·Granted Mar 18, 2014·3 cites·20 claims
- 1972US7456838B1System and method for converting a vertex program to a binary format capable of being executed by a hardware graphics pipelineNVIDIA CORP·Filed 2005·Granted Nov 25, 2008·5 cites·16 claims
- 2070US7719545B1System and method for converting a vertex program to a binary format capable of being executed by a hardware graphics pipelineNVIDIA CORP·Filed 2007·Granted May 18, 2010·4 cites·18 claims
- 2166US8850436B2Opcode-specified predicatable warp post-synchronizationFAHS BRIAN·Filed 2010·Granted Sep 30, 2014·2 cites·22 claims
- 2263US7755634B1System, method and computer program product for branching during programmable vertex processingNVIDIA CORP·Filed 2005·Granted Jul 13, 2010·2 cites·23 claims
- 2352US9195460B1Using condition codes in the presence of non-numeric valuesGLANVILLE ROBERT STEVEN·Filed 2006·Granted Nov 24, 2015·1 cites·18 claims
- 2452US9142005B2Efficient placement of texture barrier instructionsLUKYANOV MAXIM·Filed 2012·Granted Sep 22, 2015·1 cites·21 claims
- 2540US2013166882A1Methods and apparatus for scheduling instructions without instruction decodeCHOQUETTE JACK HILAIRE·Filed 2011·Application pending·0 cites
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