Inventor · disambiguated record
Krishnan Balakrishnan
Also filed as: BALAKRISHNAN KRISHNAN
9 granted patents·90 citations·filing 2019–2024
87Inventor score
Top patents by PatentIndex Score
9 records- 0197US11283459B1Calibration of a time-to-digital converter using a virtual phase-locked loopSKYWORKS SOLUTIONS INC·Filed 2021·Granted Mar 22, 2022·24 cites·20 claims
- 0297US10727845B1Use of a virtual clock in a PLL to maintain a closed loop systemSILICON LAB INC·Filed 2019·Granted Jul 28, 2020·33 cites·22 claims
- 0396US10727844B1Reference clock frequency change handling in a phase-locked loopSILICON LAB INC·Filed 2019·Granted Jul 28, 2020·18 cites·21 claims
- 0495US11563441B2Calibration of a time-to-digital converter using a virtual phase-locked loopSKYWORKS SOLUTIONS INC·Filed 2022·Granted Jan 24, 2023·6 cites·20 claims
- 0588US11888493B2Calibration of a time-to-digital converter using a virtual phase-locked loopSKYWORKS SOLUTIONS INC·Filed 2022·Granted Jan 30, 2024·1 cites·20 claims
- 0681US11526135B2Using time-to-digital converters to delay signals with high accuracy and large rangeSKYWORKS SOLUTIONS INC·Filed 2019·Granted Dec 13, 2022·3 cites·20 claims
- 0780US12019406B2Using time-to-digital converters to delay signals with high accuracy and large rangeSKYWORKS SOLUTIONS INC·Filed 2022·Granted Jun 25, 2024·1 cites·18 claims
- 0880US10651862B1Locking a PLL to the nearest edge of the input clock when the input clock is divided down before use in the PLLSILICON LAB INC·Filed 2019·Granted May 12, 2020·4 cites·20 claims
- 0971US12436504B2Using time-to-digital converters to delay signals with high accuracy and large rangeSKYWORKS SOLUTIONS INC·Filed 2024·Granted Oct 7, 2025·0 cites·19 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →