Inventor · disambiguated record
Ashok K. Kapoor
Also filed as: KAPOOR ASHOK · KAPOOR ASHOK K · KAPOOR ASHOK KUMAR
125 granted patents·20 pending applications·4,782 citations·filing 1982–2016
99Inventor score
Files withLSI LOGIC CORP68DSM SOLUTIONS INC19SUVOLTA INC13NAT SEMICONDUCTOR CORP11SEMI SOLUTIONS LLC8
Top patents by PatentIndex Score
145 records- 0198US5777360AHexagonal field programmable gate array architectureLSI LOGIC CORP·Filed 1995·Granted Jul 7, 1998·338 cites·49 claims
- 0297US5822214ACAD for hexagonal architectureLSI LOGIC CORP·Filed 1995·Granted Oct 13, 1998·297 cites·5 claims
- 0396US6407434B1Hexagonal architectureLSI LOGIC CORP·Filed 1995·Granted Jun 18, 2002·245 cites·4 claims
- 0496US5784328AMemory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM arrayLSI LOGIC CORP·Filed 1996·Granted Jul 21, 1998·209 cites·18 claims
- 0596US5650653AMicroelectronic integrated circuit including triangular CMOS "nand" gate deviceLSI LOGIC CORP·Filed 1995·Granted Jul 22, 1997·175 cites·47 claims
- 0695US7683433B2Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistorsSEMI SOLUTION LLC·Filed 2006·Granted Mar 23, 2010·50 cites·49 claims
- 0795US5498558AIntegrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making sameLSI LOGIC CORP·Filed 1994·Granted Mar 12, 1996·109 cites·20 claims
- 0895US5470801ALow dielectric constant insulation layer for integrated circuit structure and method of making sameLSI LOGIC CORP·Filed 1993·Granted Nov 28, 1995·176 cites·21 claims
- 0994US7592841B2Circuit configurations having four terminal JFET devicesDSM SOLUTIONS INC·Filed 2006·Granted Sep 22, 2009·25 cites·21 claims
- 1094US5982659AMemory cell capable of storing more than two logic states by using different via resistancesLSI LOGIC CORP·Filed 1996·Granted Nov 9, 1999·128 cites·19 claims
- 1194US5663076AAutomating photolithography in the fabrication of integrated circuitsLSI LOGIC CORP·Filed 1995·Granted Sep 2, 1997·101 cites·19 claims
- 1293US7898297B2Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuitsSEMI SOLUTION LLC·Filed 2007·Granted Mar 1, 2011·34 cites·7 claims
- 1393US5973376AArchitecture having diamond shaped or parallelogram shaped cellsLSI LOGIC CORP·Filed 1995·Granted Oct 26, 1999·157 cites·9 claims
- 1493US5742086AHexagonal DRAM arrayLSI LOGIC CORP·Filed 1995·Granted Apr 21, 1998·162 cites·40 claims
- 1592US5640049AMetal interconnect structures for use with integrated circuit devices to form integrated circuit structuresLSI LOGIC CORP·Filed 1995·Granted Jun 17, 1997·116 cites·16 claims
- 1691US7453107B1Method for applying a stress layer to a semiconductor device and device formed therefromDSM SOLUTIONS INC·Filed 2007·Granted Nov 18, 2008·17 cites·20 claims
- 1791US5889329ATri-directional interconnect architecture for SRAMLSI LOGIC CORP·Filed 1995·Granted Mar 30, 1999·135 cites·65 claims
- 1890US7586155B2Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistorsSEMI SOLUTIONS LLC·Filed 2007·Granted Sep 8, 2009·16 cites·14 claims
- 1990US7569873B2Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloysDSM SOLUTIONS INC·Filed 2005·Granted Aug 4, 2009·12 cites·66 claims
- 2090US7224205B2Apparatus and method for improving drive-strength and leakage of deep submicron MOS transistorsSEMI SOLUTIONS LLC·Filed 2005·Granted May 29, 2007·17 cites·12 claims
- 2190US5756395AProcess for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structuresLSI LOGIC CORP·Filed 1995·Granted May 26, 1998·108 cites·17 claims
- 2290US5719733AESD protection for deep submicron CMOS devices with minimum tradeoff for latchup behaviorLSI LOGIC CORP·Filed 1995·Granted Feb 17, 1998·102 cites·40 claims
- 2390US5045916AExtended silicide and external contact technologyFAIRCHILD SEMICONDUCTOR·Filed 1989·Granted Sep 3, 1991·77 cites·12 claims
- 2489US8048732B2Method for reducing leakage current and increasing drive current in a metal-oxide semiconductor (MOS) transistorSEMI SOLUTIONS LLC·Filed 2010·Granted Nov 1, 2011·10 cites·20 claims
- 2589US5166767ASidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layerNAT SEMICONDUCTOR CORP·Filed 1989·Granted Nov 24, 1992·95 cites·19 claims
- 2689US4640004AMethod and structure for inhibiting dopant out-diffusionFAIRCHILD CAMERA INSTR CO·Filed 1984·Granted Feb 3, 1987·44 cites·29 claims
- 2788US5872380AHexagonal sense cell architectureLSI LOGIC CORP·Filed 1995·Granted Feb 16, 1999·106 cites·27 claims
- 2887US7560755B2Self aligned gate JFET structure and methodDSM SOLUTIONS INC·Filed 2006·Granted Jul 14, 2009·12 cites·35 claims
- 2987US5864172ALow dielectric constant insulation layer for integrated circuit structure and method of making sameLSI LOGIC CORP·Filed 1996·Granted Jan 26, 1999·70 cites·9 claims
- 3086US5494859ALow dielectric constant insulation layer for integrated circuit structure and method of making sameLSI LOGIC CORP·Filed 1994·Granted Feb 27, 1996·97 cites·14 claims
- 3185US5877045AMethod of forming a planar surface during multi-layer interconnect formation by a laser-assisted dielectric depositionLSI LOGIC CORP·Filed 1996·Granted Mar 2, 1999·73 cites·6 claims
- 3284US7691702B2Method of manufacture of an apparatus for increasing stability of MOS memory cellsSEMI SOLUTIONS LLC·Filed 2008·Granted Apr 6, 2010·6 cites·13 claims
- 3384US6529400B1Source pulsed, dynamic threshold complementary metal oxide semiconductor static RAM cellsLSI LOGIC CORP·Filed 2000·Granted Mar 4, 2003·35 cites·12 claims
- 3483US9012276B2Variation resistant MOSFETs with superior epitaxial propertiesGOLD STANDARD SIMULATIONS LTD·Filed 2014·Granted Apr 21, 2015·7 cites·18 claims
- 3583US7474125B2Method of producing and operating a low power junction field effect transistorDSM SOLUTIONS INC·Filed 2006·Granted Jan 6, 2009·8 cites·16 claims
- 3682US5650648AIntegrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making sameLSI LOGIC CORP·Filed 1995·Granted Jul 22, 1997·43 cites·10 claims
- 3781US7687834B2Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloysSUVOLTA INC·Filed 2008·Granted Mar 30, 2010·5 cites·57 claims
- 3881US6861739B1Minimum metal consumption power distribution network on a bonded dieLSI LOGIC CORP·Filed 2001·Granted Mar 1, 2005·30 cites·24 claims
- 3981US5521108AProcess for making a conductive germanium/silicon member with a roughened surface thereon suitable for use in an integrated circuit structureLSI LOGIC CORP·Filed 1993·Granted May 28, 1996·41 cites·22 claims
- 4081US4829363AStructure for inhibiting dopant out-diffusionFAIRCHILD CAMERA INSTR CO·Filed 1988·Granted May 9, 1989·37 cites·17 claims
- 4180US7986167B2Circuit configurations having four terminal devicesSUVOLTA INC·Filed 2010·Granted Jul 26, 2011·4 cites·20 claims
- 4280US5780350AMOSFET device with improved LDD region and method of making sameLSI LOGIC CORP·Filed 1997·Granted Jul 14, 1998·46 cites·15 claims
- 4379US7525136B2JFET device with virtual source and drain link regions and method of fabricationDSM SOLUTIONS INC·Filed 2007·Granted Apr 28, 2009·8 cites·14 claims
- 4478US7943971B1Junction field effect transistor (JFET) structure having top-to-bottom gate tie and method of manufactureSUVOLTA INC·Filed 2008·Granted May 17, 2011·5 cites·1 claims
- 4578US6109775AMethod for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereonLSI LOGIC CORP·Filed 1997·Granted Aug 29, 2000·60 cites·18 claims
- 4678US5789770AHexagonal architecture with triangular shaped cellsLSI LOGIC CORP·Filed 1995·Granted Aug 4, 1998·53 cites·41 claims
- 4777US5808330APolydirectional non-orthoginal three layer interconnect architectureLSI LOGIC CORP·Filed 1995·Granted Sep 15, 1998·54 cites·12 claims
- 4877US5472901AProcess for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional stepsLSI LOGIC CORP·Filed 1994·Granted Dec 5, 1995·48 cites·13 claims
- 4976US5985746AProcess for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and resulting productLSI LOGIC CORP·Filed 1996·Granted Nov 16, 1999·53 cites·13 claims
- 5076US5808932AMemory system which enables storage and retrieval of more than two states in a memory cellLSI LOGIC CORP·Filed 1996·Granted Sep 15, 1998·39 cites·18 claims
Showing the top 50 of 145 patent records by PatentIndex Score.
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