Inventor · disambiguated record
Paul A. Rabidoux
Also filed as: RABIDOUX PAUL A
38 granted patents·2,023 citations·filing 1996–2004
98Inventor score
Top patents by PatentIndex Score
38 records- 0199US6440801B1Structure for folded architecture pillar memory cellIBM·Filed 2000·Granted Aug 27, 2002·199 cites·13 claims
- 0298US6114725AStructure for folded architecture pillar memory cellIBM·Filed 1998·Granted Sep 5, 2000·160 cites·11 claims
- 0395US6387783B1Methods of T-gate fabrication using a hybrid resistIBM·Filed 1999·Granted May 14, 2002·134 cites·18 claims
- 0495US6338934B1Hybrid resist based on photo acid/photo base blendingIBM·Filed 1999·Granted Jan 15, 2002·126 cites·29 claims
- 0595US6096598AMethod for forming pillar memory cells and device formed therebyIBM·Filed 1998·Granted Aug 1, 2000·200 cites·23 claims
- 0695US5945707ADRAM cell with grooved transfer deviceIBM·Filed 1998·Granted Aug 31, 1999·127 cites·15 claims
- 0792US6319651B1Acid sensitive ARC and method of useIBM·Filed 2000·Granted Nov 20, 2001·36 cites·5 claims
- 0892US6037194AMethod for making a DRAM cell with grooved transfer deviceIBM·Filed 1999·Granted Mar 14, 2000·82 cites·35 claims
- 0991US6221562B1Resist image reversal by means of spun-on-glassIBM·Filed 1998·Granted Apr 24, 2001·113 cites·1 claims
- 1091US6110653AAcid sensitive ARC and method of useIBM·Filed 1999·Granted Aug 29, 2000·72 cites·16 claims
- 1189US6114082AFrequency doubling hybrid photoresist having negative and positive tone components and method of preparing the sameIBM·Filed 1996·Granted Sep 5, 2000·81 cites·21 claims
- 1288US6627361B2Assist features for contact hole mask patternsIBM·Filed 2001·Granted Sep 30, 2003·29 cites·17 claims
- 1388US6531724B1Borderless gate structuresIBM·Filed 2000·Granted Mar 11, 2003·37 cites·8 claims
- 1486US7176089B2Vertical dual gate field effect transistorIBM·Filed 2004·Granted Feb 13, 2007·36 cites·7 claims
- 1581US6007968AMethod for forming features using frequency doubling hybrid resist and device formed therebyIBM·Filed 1997·Granted Dec 28, 1999·47 cites·15 claims
- 1678US6440635B1Low “K” factor hybrid photoresistIBM·Filed 2000·Granted Aug 27, 2002·16 cites·8 claims
- 1777US6798017B2Vertical dual gate field effect transistorIBM·Filed 2001·Granted Sep 28, 2004·20 cites·37 claims
- 1877US6184041B1Fused hybrid resist shapes as a means of modulating hybrid resist space widthIBM·Filed 1998·Granted Feb 6, 2001·36 cites·21 claims
- 1977US6150256AMethod for forming self-aligned featuresIBM·Filed 1998·Granted Nov 21, 2000·49 cites·53 claims
- 2076US6303272B1Process for self-alignment of sub-critical contacts to wiringIBM·Filed 1998·Granted Oct 16, 2001·50 cites·18 claims
- 2175US6207514B1Method for forming borderless gate structures and apparatus formed therebyIBM·Filed 1999·Granted Mar 27, 2001·46 cites·28 claims
- 2272US6194268B1Printing sublithographic images using a shadow mandrel and off-axis exposureIBM·Filed 1998·Granted Feb 27, 2001·41 cites·48 claims
- 2368US6200726B1Optimization of space width for hybrid photoresistIBM·Filed 1998·Granted Mar 13, 2001·33 cites·19 claims
- 2466US6190829B1Low “K” factor hybrid photoresistIBM·Filed 1996·Granted Feb 20, 2001·24 cites·10 claims
- 2565US6284439B1Method of producing an integrated circuit chip using low “k” factor hybrid photoresist and apparatus formed therebyIBM·Filed 1998·Granted Sep 4, 2001·24 cites·12 claims
- 2664US6313492B1Integrated circuit chip produced by using frequency doubling hybrid photoresistIBM·Filed 1998·Granted Nov 6, 2001·22 cites·12 claims
- 2763US6014422AMethod for varying x-ray hybrid resist space dimensionsINTERNAITONAL BUSINESS MACHINE·Filed 1998·Granted Jan 11, 2000·21 cites·17 claims
- 2863US5956597AMethod for producing SOI & non-SOI circuits on a single waferIBM·Filed 1997·Granted Sep 21, 1999·28 cites·20 claims
- 2961US6100172AMethod for forming a horizontal surface spacer and devices formed therebyIBM·Filed 1998·Granted Aug 8, 2000·24 cites·19 claims
- 3060US6221704B1Process for fabricating short channel field effect transistor with a highly conductive gateIBM·Filed 1998·Granted Apr 24, 2001·19 cites·33 claims
- 3159US6210866B1Method for forming features using self-trimming by selective etch and device formed therebyIBM·Filed 1998·Granted Apr 3, 2001·22 cites·18 claims
- 3257US6372412B1Method of producing an integrated circuit chip using frequency doubling hybrid photoresist and apparatus formed therebyIBM·Filed 1998·Granted Apr 16, 2002·16 cites·13 claims
- 3355US6245488B1Method for forming features using frequency doubling hybrid resist and device formed therebyIBM·Filed 1999·Granted Jun 12, 2001·15 cites·11 claims
- 3447US6017810AProcess for fabricating field effect transistor with a self-aligned gate to device isolationIBM·Filed 1998·Granted Jan 25, 2000·10 cites·14 claims
- 3545US6759315B1Method for selective trimming of gate structures and apparatus formed therebyIBM·Filed 1999·Granted Jul 6, 2004·8 cites·31 claims
- 3644US6426175B2Fabrication of a high density long channel DRAM gate with or without a grooved gateIBM·Filed 1999·Granted Jul 30, 2002·12 cites·19 claims
- 3744US6277543B1Method for forming features using frequency doubling hybrid resist and device formed therebyIBM·Filed 1999·Granted Aug 21, 2001·8 cites·4 claims
- 3843US6815737B2Method for selective trimming of gate structures and apparatus formed therebyIBM·Filed 2004·Granted Nov 9, 2004·0 cites·17 claims
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