Inventor · disambiguated record
Leonid Alexander Broukhis
Also filed as: BROUKHIS LEONID A · BROUKHIS LEONID ALEXANDER
10 granted patents·3 pending applications·93 citations·filing 2000–2018
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
13 records- 0183US7548842B2Scalable system for simulation and emulation of electronic circuits using asymmetrical evaluation and canvassing instruction processorsEVE S A·Filed 2006·Granted Jun 16, 2009·18 cites·11 claims
- 0278US10962595B1Efficient realization of coverage collection in emulationSYNOPSYS INC·Filed 2018·Granted Mar 30, 2021·3 cites·25 claims
- 0376US8359186B2Method for delay immune and accelerated evaluation of digital circuits by compiling asynchronous completion handshaking meansGANESAN SUBBU·Filed 2007·Granted Jan 22, 2013·12 cites·8 claims
- 0468US7509602B2Compact processor element for a scalable digital logic verification and emulation systemEVE S A·Filed 2006·Granted Mar 24, 2009·6 cites·3 claims
- 0568US6470480B2Tracing different states reached by a signal in a functional verification systemTHARAS SYSTEMS INC·Filed 2000·Granted Oct 22, 2002·15 cites·9 claims
- 0665US6629297B2Tracing the change of state of a signal in a functional verification systemTHARAS SYSTEMS INC·Filed 2000·Granted Sep 30, 2003·13 cites·13 claims
- 0764US6691287B2Functional verification systemTHARAS SYSTEMS INC·Filed 2000·Granted Feb 10, 2004·12 cites·32 claims
- 0863US10325046B2Formal method for clock tree analysis and optimizationSYNOPSYS INC·Filed 2017·Granted Jun 18, 2019·1 cites·20 claims
- 0959US6480988B2Functional verification of both cycle-based and non-cycle based designsTHARAS SYSTEMS INC·Filed 2000·Granted Nov 12, 2002·8 cites·19 claims
- 1055US6625786B2Run-time controller in a functional verification systemTHARAS SYSTEMS INC·Filed 2000·Granted Sep 23, 2003·5 cites·23 claims
- 1142US2006277428A1A system and method for simulation of electronic circuits generating clocks and delaying the execution of instructions in a plurality of processorsTHARAS SYSTEMS INC·Filed 2006·Application pending·0 cites
- 1242US2007044079A1A system and method for compiling a description of an electronic circuit to instructions adapted to execute on a plurality of processorsTHARAS SYSTEMS INC·Filed 2006·Application pending·0 cites
- 1341US2006277020A1A reconfigurable system for verification of electronic circuits using high-speed serial links to connect asymmetrical evaluation and canvassing instruction processorsTHARAS SYSTEMS·Filed 2006·Application pending·0 cites
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