Inventor · disambiguated record
Terence J. Magee
Also filed as: MAGEE TERENCE · MAGEE TERENCE J
17 granted patents·3 pending applications·120 citations·filing 2005–2022
93Inventor score
Top patents by PatentIndex Score
20 records- 0193US7437500B2Configurable high-speed memory interface subsystemLSI CORP·Filed 2005·Granted Oct 14, 2008·35 cites·18 claims
- 0283US10009197B1Method and apparatus for intersymbol interference compensationXILINX INC·Filed 2016·Granted Jun 26, 2018·9 cites·20 claims
- 0382US9324409B1Method and apparatus for gating a strobe signal from a memory and subsequent tracking of the strobe signal over timeXILINX INC·Filed 2014·Granted Apr 26, 2016·9 cites·20 claims
- 0481US10103718B1Recalibration of source synchronous systemsXILINX INC·Filed 2017·Granted Oct 16, 2018·4 cites·20 claims
- 0581US8453096B2Non-linear common coarse delay system and method for delaying data strobeMAGEE TERENCE J·Filed 2011·Granted May 28, 2013·9 cites·18 claims
- 0680US7454303B2System and method for compensating for PVT variation effects on the delay line of a clock signalLSI LOGIC CORP·Filed 2006·Granted Nov 18, 2008·12 cites·21 claims
- 0778US9281049B1Read clock forwarding for multiple source-synchronous memory interfacesXILINX INC·Filed 2014·Granted Mar 8, 2016·7 cites·20 claims
- 0878US7865661B2Configurable high-speed memory interface subsystemLSI CORP·Filed 2008·Granted Jan 4, 2011·9 cites·20 claims
- 0974US9331701B1Receivers and methods of enabling the calibration of circuits receiving input dataXILINX INC·Filed 2014·Granted May 3, 2016·4 cites·18 claims
- 1072US9557766B1High-speed serial data interface for a physical layer interfaceXILINX INC·Filed 2014·Granted Jan 31, 2017·3 cites·20 claims
- 1170US9330749B1Dynamic selection of output delay in a memory control deviceXILINX INC·Filed 2014·Granted May 3, 2016·4 cites·20 claims
- 1269US7605628B2System for glitch-free delay updates of a standard cell-based programmable delayLSI CORP·Filed 2007·Granted Oct 20, 2009·6 cites·20 claims
- 1368US9355696B1Calibration in a control device receiving from a source synchronous interfaceXILINX INC·Filed 2014·Granted May 31, 2016·2 cites·20 claims
- 1463US7969799B2Multiple memory standard physical layer macro functionLSI CORP·Filed 2008·Granted Jun 28, 2011·5 cites·22 claims
- 1557US8743634B2Generic low power strobe based system and method for interfacing memory controller and source synchronous memoryMAGEE TERENCE J·Filed 2011·Granted Jun 3, 2014·2 cites·11 claims
- 1655US11789641B2Three dimensional circuit systems and methods having memory hierarchiesINTEL CORP·Filed 2021·Granted Oct 17, 2023·0 cites·23 claims
- 1751US2023123826A1Source Synchronous Partition of an SDRAM Controller SubsystemINTEL CORP·Filed 2022·Application pending·0 cites
- 1849US2023140547A1Input Output Banks of a Programmable Logic DeviceINTEL CORP·Filed 2022·Application pending·0 cites
- 1946US2023118912A1Techniques For Synchronous Accesses To Storage CircuitsINTEL CORP·Filed 2022·Application pending·0 cites
- 2033US9224444B1Method and apparatus for VT invariant SDRAM write leveling and fast rank switchingXILINX INC·Filed 2014·Granted Dec 29, 2015·0 cites·20 claims
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