Inventor

PATEL BAIJU V

US73 patents

⚠️ This page may combine multiple inventors who share the name “PATEL BAIJU V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PATEL BAIJU V

INTEL CORP

Method for securing communications in a pre-boot environment

Processor extensions to protect stacks during ring transitions

Secure public cloud with protected guest-verified host control

Creating stack position dependent cryptographic return address to mitigate return oriented programming attacks

Encoded inline capabilities

Technique and apparatus for processing cryptographic services of data in a network system

Method and apparatus for controlling available capabilities of a device

Function as a service (FaaS) system enhancements

Encryption interface

Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers

Mechanism to emulate user-level multithreading on an OS-sequestered sequencer

Method and apparatus for strong authentication and proximity-based access retention

Processor extensions to protect stacks during ring transitions

Processor extensions to protect stacks during ring transitions

Cryptographic memory ownership table for secure public cloud

System, apparatus and method for page granular, software controlled multiple key memory encryption

Secure public cloud with protected guest-verified host control

Hardware apparatuses and methods to switch shadow stack pointers

Multi-tenant encryption for storage class memory

Defining virtualized page attributes based on guest page attributes

Sequencer address management

System for address mapping and translation protection

Apparatus, system, and method for persistent user-level thread

Processor extensions to protect stacks during ring transitions

Cryptographic memory ownership table for secure public cloud

System for address mapping and translation protection

Secure public cloud with protected guest-verified host control

Virtual machine manager for address mapping and translation protection

Return address overflow buffer

Enhance memory access permission based on per-page current privilege level

Systems and methods for preventing unauthorized stack pivoting

Processors, methods, systems, and instructions to protect shadow stacks

Providing isolation in virtualized systems using trust domains

Processors, methods, systems, and instructions to protect shadow stacks

Cryptographic memory ownership table for secure public cloud

Multi-tenant encryption for storage class memory

Method and system for correlating data from multiple sources without compromising confidentiality requirements

Encryption interface

Hardware apparatuses and methods to switch shadow stack pointers

System, apparatus and method for page granular, software controlled multiple key memory encryption

IBM

ATM cell scheduler

Apparatus for connecting two fiber distributed data interface rings

Method and apparatus for interoperation of FDDI-I and FDDI-II networks

CHINYA GAUTHAM

Transparent support for operating system services for a sequestered sequencer

Apparatus, system, and method for persistent user-level thread

WANG HONG

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

PATEL BAIJU V

Managing and implementing metadata in central processing unit using register extensions

SAHITA RAVI L

System for address mapping and translation protection

HANKINS RICHARD A

Structured exception handling for application-managed thread units

VAN DYKE DON A

Context state management for processor feature sets