Inventor · disambiguated record
Richard Q. Williams
Also filed as: WILLIAMS RICHARD Q · WILLIAMS RICHARD QUIMBY
75 granted patents·8 pending applications·2,258 citations·filing 1996–2019
99Inventor score
Top patents by PatentIndex Score
83 records- 0199US6921982B2FET channel having a strained lattice structure along multiple surfacesIBM·Filed 2003·Granted Jul 26, 2005·327 cites·23 claims
- 0298US7681628B2Dynamic control of back gate bias in a FinFET SRAM cellIBM·Filed 2006·Granted Mar 23, 2010·131 cites·13 claims
- 0397US6271059B1Chip interconnection structure using stub terminalsIBM·Filed 1999·Granted Aug 7, 2001·274 cites·7 claims
- 0496US9601570B1Structure for reduced source and drain contact to gate stack capacitanceIBM·Filed 2016·Granted Mar 21, 2017·10 cites·12 claims
- 0596US7198990B2Method for making a FET channelIBM·Filed 2005·Granted Apr 3, 2007·28 cites·9 claims
- 0695US7337420B2Methodology for layout-based modulation and optimization of nitride liner stress effect in compact modelsIBM·Filed 2005·Granted Feb 26, 2008·61 cites·38 claims
- 0795US7250351B2Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistorsIBM·Filed 2005·Granted Jul 31, 2007·24 cites·19 claims
- 0895US6498056B1Apparatus and method for antifuse with electrostatic assistIBM·Filed 2000·Granted Dec 24, 2002·69 cites·17 claims
- 0995US6054745ANonvolatile memory cell using microelectromechanical deviceIBM·Filed 1999·Granted Apr 25, 2000·114 cites·31 claims
- 1094US10546936B2Structure for reduced source and drain contact to gate stack capacitanceIBM·Filed 2019·Granted Jan 28, 2020·6 cites·13 claims
- 1194US6396120B1Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and applicationIBM·Filed 2000·Granted May 28, 2002·84 cites·26 claims
- 1293US7538391B2Curved FINFETsIBM·Filed 2007·Granted May 26, 2009·28 cites·10 claims
- 1393US7532501B2Semiconductor device including back-gated transistors and method of fabricating the deviceIBM·Filed 2005·Granted May 12, 2009·29 cites·16 claims
- 1493US6611050B1Chip edge interconnect apparatus and methodIBM·Filed 2000·Granted Aug 26, 2003·79 cites·16 claims
- 1592US7375000B2Discrete on-chip SOI resistorsIBM·Filed 2005·Granted May 20, 2008·19 cites·15 claims
- 1692US7102181B1Structure and method for dual-gate FET with SOI substrateIBM·Filed 2005·Granted Sep 5, 2006·21 cites·16 claims
- 1792US6114221AMethod and apparatus for interconnecting multiple circuit chipsIBM·Filed 1998·Granted Sep 5, 2000·133 cites·8 claims
- 1892US6063132AMethod for verifying design rule checking softwareIBM·Filed 1998·Granted May 16, 2000·350 cites·30 claims
- 1991US7382036B2Doped single crystal silicon silicided eFuseIBM·Filed 2005·Granted Jun 3, 2008·19 cites·15 claims
- 2090US7265005B2Structure and method for dual-gate FET with SOI substrateIBM·Filed 2005·Granted Sep 4, 2007·15 cites·26 claims
- 2189US9755030B2Method for reduced source and drain contact to gate stack capacitanceIBM·Filed 2015·Granted Sep 5, 2017·4 cites·15 claims
- 2289US9059203B2Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structureIBM·Filed 2013·Granted Jun 16, 2015·7 cites·14 claims
- 2389US7659579B2FETS with self-aligned bodies and backgate holesIBM·Filed 2006·Granted Feb 9, 2010·14 cites·12 claims
- 2488US8745571B2Analysis of compensated layout shapesLI HONGMEI·Filed 2011·Granted Jun 3, 2014·13 cites·12 claims
- 2587US7129138B1Methods of implementing and enhanced silicon-on-insulator (SOI) box structuresIBM·Filed 2005·Granted Oct 31, 2006·15 cites·11 claims
- 2686US8610211B2Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structureFURUKAWA TOSHIHARU·Filed 2010·Granted Dec 17, 2013·6 cites·20 claims
- 2786US6844609B2Antifuse with electrostatic assistIBM·Filed 2002·Granted Jan 18, 2005·30 cites·14 claims
- 2885US6433985B1ESD network with capacitor blocking elementIBM·Filed 1999·Granted Aug 13, 2002·56 cites·10 claims
- 2984US7786466B2Carbon nanotube based integrated semiconductor circuitIBM·Filed 2008·Granted Aug 31, 2010·17 cites·17 claims
- 3084US7761278B2Semiconductor device stress modeling methodologyIBM·Filed 2007·Granted Jul 20, 2010·13 cites·28 claims
- 3183US8211741B2Carbon nanotube based integrated semiconductor circuitAPPENZELLER JOERG·Filed 2011·Granted Jul 3, 2012·10 cites·4 claims
- 3283US8017934B2Carbon nanotube based integrated semiconductor circuitIBM·Filed 2010·Granted Sep 13, 2011·10 cites·19 claims
- 3382US10269905B2Structure for reduced source and drain contact to gate stack capacitanceIBM·Filed 2017·Granted Apr 23, 2019·2 cites·13 claims
- 3482US7700410B2Chip-in-slot interconnect for 3D chip stacksIBM·Filed 2007·Granted Apr 20, 2010·9 cites·8 claims
- 3581US8119474B2High performance capacitors in planar back gates CMOSBRYANT ANDRES·Filed 2010·Granted Feb 21, 2012·5 cites·19 claims
- 3681US8112729B2Method and system for selective stress enablement in simulation modelingTONTI WILLIAM ROBERT·Filed 2009·Granted Feb 7, 2012·14 cites·25 claims
- 3781US8037433B2System and methodology for determining layout-dependent effects in ULSI simulationIBM·Filed 2008·Granted Oct 11, 2011·11 cites·30 claims
- 3881US7462916B2Semiconductor devices having torsional stressesIBM·Filed 2006·Granted Dec 9, 2008·10 cites·4 claims
- 3980US9646124B2Modeling transistor performance considering non-uniform local layout effectsIBM·Filed 2015·Granted May 9, 2017·3 cites·20 claims
- 4079US8453100B2Circuit analysis using transverse bucketsCHIDAMBARRAO DURESETI·Filed 2010·Granted May 28, 2013·5 cites·20 claims
- 4179US7627840B2Method for soft error modeling with double current pulseIBM·Filed 2006·Granted Dec 1, 2009·11 cites·20 claims
- 4276US7709313B2High performance capacitors in planar back gates CMOSIBM·Filed 2005·Granted May 4, 2010·5 cites·32 claims
- 4376US7572724B2Doped single crystal silicon silicided eFuseIBM·Filed 2008·Granted Aug 11, 2009·5 cites·20 claims
- 4475US7345334B2Integrated circuit (IC) with high-Q on-chip discrete capacitorsIBM·Filed 2005·Granted Mar 18, 2008·5 cites·7 claims
- 4575US7217604B2Structure and method for thin box SOI deviceIBM·Filed 2005·Granted May 15, 2007·6 cites·14 claims
- 4675US6445029B1NVRAM array device with enhanced write and eraseIBM·Filed 2000·Granted Sep 3, 2002·20 cites·7 claims
- 4771US8806419B2Apparatus for modeling of FinFET width quantizationIBM·Filed 2013·Granted Aug 12, 2014·2 cites·9 claims
- 4871US8799848B1Methods for modeling of FinFET width quantizationIBM·Filed 2013·Granted Aug 5, 2014·2 cites·12 claims
- 4971US7934181B2Method and apparatus for improving SRAM cell stability by using boosted word linesIBM·Filed 2008·Granted Apr 26, 2011·6 cites·15 claims
- 5070US6022770ANVRAM utilizing high voltage TFT device and method for making the sameIBM·Filed 1998·Granted Feb 8, 2000·25 cites·18 claims
Showing the top 50 of 83 patent records by PatentIndex Score.
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