Inventor · disambiguated record
Harry Ray Fair, Iii
Also filed as: FAIR HARRY R · FAIR III HARRY R · FAIR III HARRY RAY
8 granted patents·77 citations·filing 1998–2010
84Inventor score
Files withCOMPAQ COMPUTER CORP2HEWLETT PACKARD DEVELOPMENT CO2SUN MICROSYSTEMS INC2COMPAQ INFORMATION TECHNOLOGIE1GILLESPIE KEVIN M1
Top patents by PatentIndex Score
8 records- 0184US6794902B2Virtual ground circuitSUN MICROSYSTEMS INC·Filed 2002·Granted Sep 21, 2004·40 cites·22 claims
- 0271US6675288B2Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register listHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Jan 6, 2004·16 cites·16 claims
- 0351US7206916B2Partial address compares stored in translation lookaside bufferSUN MICROSYSTEMS INC·Filed 2004·Granted Apr 17, 2007·5 cites·21 claims
- 0442US6877142B2Timing verifier for MOS devices and related methodHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Apr 5, 2005·0 cites·18 claims
- 0541US8850278B2Fault tolerant scannable glitch latchGILLESPIE KEVIN M·Filed 2010·Granted Sep 30, 2014·0 cites·21 claims
- 0640US6405304B1Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register listCOMPAQ INFORMATION TECHNOLOGIE·Filed 1998·Granted Jun 11, 2002·12 cites·8 claims
- 0729US6473888B1Timing verifier for MOS devices and related methodCOMPAQ COMPUTER CORP·Filed 1998·Granted Oct 29, 2002·4 cites·10 claims
- 0825US6438732B1Method and apparatus for modeling gate capacitance of symmetrically and asymmetrically sized differential cascode voltage swing logic (DCVSL)COMPAQ COMPUTER CORP·Filed 1999·Granted Aug 20, 2002·0 cites·3 claims
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