Inventor · disambiguated record
Madhav Desai
Also filed as: DESAI MADHAV · DESAI MADHAV P
4 granted patents·1 pending application·29 citations·filing 1998–2005
72Inventor score
Technology areasG06F
Top patents by PatentIndex Score
5 records- 0166US7260797B2Method and apparatus for estimating parasitic capacitanceSYNOPSYS INC·Filed 2004·Granted Aug 21, 2007·15 cites·24 claims
- 0242US6877142B2Timing verifier for MOS devices and related methodHEWLETT PACKARD DEVELOPMENT CO·Filed 2002·Granted Apr 5, 2005·0 cites·18 claims
- 0338US2006247909A1System and method for emulating a logic circuit design using programmable logic devicesDESAI MADHAV P·Filed 2005·Application pending·0 cites
- 0433US6606587B1Method and apparatus for estimating elmore delays within circuit designsHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Aug 12, 2003·10 cites·16 claims
- 0529US6473888B1Timing verifier for MOS devices and related methodCOMPAQ COMPUTER CORP·Filed 1998·Granted Oct 29, 2002·4 cites·10 claims
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