Inventor · disambiguated record
Chee Tee Chua
Also filed as: CHUA CHEE T · CHUA CHEE TEE
9 granted patents·426 citations·filing 1998–2009
90Inventor score
Top patents by PatentIndex Score
9 records- 0196US6348385B1Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constantCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Feb 19, 2002·128 cites·12 claims
- 0290US6121130ALaser curing of spin-on dielectric thin filmsCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Sep 19, 2000·118 cites·20 claims
- 0383US8161355B2Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic processFUNG STEPHEN·Filed 2009·Granted Apr 17, 2012·18 cites·24 claims
- 0482US6140197AMethod of making spiral-type RF inductors having a high quality factor (Q)CHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Oct 31, 2000·61 cites·19 claims
- 0581US6221727B1Method to trap air at the silicon substrate for improving the quality factor of RF inductors in CMOS technologyCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Apr 24, 2001·66 cites·26 claims
- 0678US7573081B2Method to fabricate horizontal air columns underneath metal inductorCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Aug 11, 2009·7 cites·6 claims
- 0771US6284610B1Method to reduce compressive stress in the silicon substrate during silicidationCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Sep 4, 2001·19 cites·31 claims
- 0842US7105420B1Method to fabricate horizontal air columns underneath metal inductorUNIV SINGAPORE·Filed 1999·Granted Sep 12, 2006·9 cites·19 claims
- 0930US8081521B2Two bits per cell non-volatile memory architectureCHUA CHEE T·Filed 2009·Granted Dec 20, 2011·0 cites·14 claims
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