Inventor · disambiguated record
Eric F. Dellinger
Also filed as: DELLINGER ERIC · DELLINGER ERIC F · DELLINGER ERIC FORD
23 granted patents·4 pending applications·1,385 citations·filing 1995–2023
97Inventor score
Top patents by PatentIndex Score
27 records- 0198US9859896B1Distributed multi-die routing in a multi-chip moduleXILINX INC·Filed 2015·Granted Jan 2, 2018·52 cites·20 claims
- 0296US7770144B2Modular array defined by standard cell logicDELLINGER ERIC·Filed 2003·Granted Aug 3, 2010·195 cites·12 claims
- 0396US6613611B1ASIC routing architecture with variable number of custom masksLIGHTSPEED SEMICONDUCTOR CORP·Filed 2000·Granted Sep 2, 2003·125 cites·16 claims
- 0495US6457164B1Hetergeneous method for determining module placement in FPGAsXILINX INC·Filed 2000·Granted Sep 24, 2002·103 cites·17 claims
- 0595US5659484AFrequency driven layout and method for field programmable gate arraysXILINX INC·Filed 1995·Granted Aug 19, 1997·317 cites·23 claims
- 0693US12307217B1Dynamic adjustment of floating point exponent bias for exponent compressionXILINX INC·Filed 2021·Granted May 20, 2025·3 cites·20 claims
- 0790US11216275B1Converting floating point data into integer data using a dynamically adjusted scale factorXILINX INC·Filed 2019·Granted Jan 4, 2022·6 cites·20 claims
- 0882US6696856B1Function block architecture with variable drive strengthsLIGHTSPEED SEMICONDUCTOR CORP·Filed 2001·Granted Feb 24, 2004·26 cites·18 claims
- 0982US6216258B1FPGA modules parameterized by expressionsXILINX INC·Filed 1998·Granted Apr 10, 2001·84 cites·20 claims
- 1082US5648913AFrequency driven layout system and method for field programmable gate arraysXILINX INC·Filed 1995·Granted Jul 15, 1997·97 cites·14 claims
- 1181US10042806B2System-level interconnect ring for a programmable integrated circuitXILINX INC·Filed 2016·Granted Aug 7, 2018·3 cites·20 claims
- 1280US6292925B1Context-sensitive self implementing modulesXILINX INC·Filed 1998·Granted Sep 18, 2001·90 cites·37 claims
- 1378US6243851B1Heterogeneous method for determining module placement in FPGAsXILINX INC·Filed 1998·Granted Jun 5, 2001·71 cites·30 claims
- 1478US6205574B1Method and system for generating a programming bitstream including identification bitsXILINX INC·Filed 1998·Granted Mar 20, 2001·84 cites·20 claims
- 1575US6260182B1Method for specifying routing in a logic module by direct module communicationXILINX INC·Filed 1998·Granted Jul 10, 2001·70 cites·32 claims
- 1671US7648912B1ASIC customization with predefined via maskDELLINGER ERIC·Filed 2006·Granted Jan 19, 2010·4 cites·10 claims
- 1765US6885043B2ASIC routing architectureLIGHTSPEED SEMICONDUCTOR CORP·Filed 2002·Granted Apr 26, 2005·12 cites·33 claims
- 1864US7102237B1ASIC customization with predefined via maskLIGHTSPEED SEMICONDUCTOR CORP·Filed 2003·Granted Sep 5, 2006·9 cites·2 claims
- 1962US6237129B1Method for constraining circuit element positions in structured layoutsXILINX INC·Filed 1998·Granted May 22, 2001·34 cites·35 claims
- 2061US2025190813A1Fine-tuning of neural networksADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 2160US2024211762A1Optimizing low precision and sparsity inference without retrainingADVANCED MICRO DEVICES INC·Filed 2022·Application pending·0 cites
- 2253US12393480B2Reclamation of memory ECC bits for error tolerant number formatsXILINX INC·Filed 2023·Granted Aug 19, 2025·0 cites·14 claims
- 2352US10715149B1Configurable logic block (CLB) internal routing architecture for enhanced local routing and clocking improvementsXILINX INC·Filed 2019·Granted Jul 14, 2020·0 cites·21 claims
- 2451US11824564B1Lossless compression using subnormal floating point valuesXILINX INC·Filed 2021·Granted Nov 21, 2023·0 cites·20 claims
- 2549US2024118868A1Multiplier block for block floating point and floating point valuesXILINX INC·Filed 2022·Application pending·0 cites
- 2648US8504950B2Modular array defined by standard cell logicDELLINGER ERIC·Filed 2010·Granted Aug 6, 2013·0 cites·12 claims
- 2743US2001001881A1Methods and media for utilizing symbolic expressions in circuit modulesFiled 2000·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →