Inventor

JIN BEEN-YIH

US80 patents

⚠️ This page may combine multiple inventors who share the name “JIN BEEN-YIH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JIN BEEN-YIH

INTEL CORP

Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers

Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow

Tri-gate transistors and methods to fabricate same

Nonplanar device with stress incorporation layer and method of fabrication

Nonplanar device with stress incorporation layer and method of fabrication

Nonplanar device with stress incorporation layer and method of fabrication

Tri-gate patterning using dual layer gate stack

Non-planar MOS structure with a strained channel region

Non-planar MOS structure with a strained channel region

Fabrication of germanium nanowire transistors

Transistor having tensile strained channel and system including same

Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications

Transistor gate electrode having conductor material layer

Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors

Field effect transistor and method of fabrication

Transistor gate electrode having conductor material layer

CMOS devices with a single work function gate electrode and method of fabrication

Isolated Germanium nanowire on Silicon fin

Strain-inducing semiconductor regions

Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method

Tri-gate transistor device with stress incorporation layer and method of fabrication

Methods for inducing strain in non-planar transistor structures

Tensile strained NMOS transistor using group III-N source/drain regions

Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow

Field effect transistor and method of fabrication

Field effect transistor and method of fabrication

Techniques for forming non-planar germanium quantum well devices

Tunneling field effect transistor using angled implants for forming asymmetric source/drain regions

Mechanism for forming a remote delta doping layer of a quantum well structure

Faceted catalytic dots for directed nanotube growth

Semiconductor channel on insulator structure

Semiconductor channel on insulator structure

Semiconductor on insulator apparatus

Transistor gate electrode having conductor material layer

Protection of three dimensional transistor structures during gate stack etch

DATTA SUMAN

Strain inducing semiconductor regions

Strain-inducing semiconductor regions

Tensile strained NMOS transistor using group III-N source/drain regions

JIN BEEN-YIH

Fabrication of germanium nanowire transistors

Method to introduce uniaxial strain in multigate nanoscale transistors by self aligned SI to SIGE conversion processes and structures formed thereby

DOYLE BRIAN S

CMOS devices with a single work function gate electrode and method of fabrication

Substrate band gap engineered multi-gate pMOS devices

MACRONIX INT CO LTD

Spin-on-glass process with controlled environment

Integrated circuit passivation process and structure

PILLARISETTY RAVI

Germanium-based quantum well devices

Apparatus and methods for improving parallel conduction in a quantum well device

KAVALIEROS JACK T

Two-dimensional condensation for uniaxially strained semiconductor fins

HARELAND SCOTT A

Tri-gate transistor device with stress incorporation layer and method of fabrication

DATT DOT OVER A SUMAN

Extreme high mobility CMOS logic

MACRONIX INTERNATIONALCO LTD

Spin-on-glass process with controlled environment