Inventor · disambiguated record
Raymond Jit-Hung Sung
Also filed as: SUNG RAYMOND J · SUNG RAYMOND JIT-HUNG · Sung raymond
11 granted patents·14 pending applications·126 citations·filing 2003–2025
89Inventor score
Top patents by PatentIndex Score
25 records- 0190US12141683B2Performance scaling for dataflow deep neural network hardware acceleratorsINTEL CORP·Filed 2021·Granted Nov 12, 2024·3 cites·20 claims
- 0284US7046522B2Method for scalable architectures in stackable three-dimensional integrated circuits and electronicsSUNG RAYMOND JIT-HUNG·Filed 2003·Granted May 16, 2006·63 cites·68 claims
- 0382US12147836B2Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning acceleratorsINTEL CORP·Filed 2021·Granted Nov 19, 2024·1 cites·31 claims
- 0482US6803782B2Arrayed processing element redundancy architectureFiled 2003·Granted Oct 12, 2004·35 cites·23 claims
- 0576US2025322218A1System and method for balancing sparsity in weights for accelerating deep neural networksINTEL CORP·Filed 2025·Application pending·0 cites
- 0674US2025036928A1Performance scaling for dataflow deep neural network hardware acceleratorsINTEL CORP·Filed 2024·Application pending·0 cites
- 0773US2025028565A1Schedule-aware dynamically reconfigurable adder tree architecture for partial sum accumulation in machine learning acceleratorsINTEL CORP·Filed 2024·Application pending·0 cites
- 0865US12367380B2System and method for balancing sparsity in weights for accelerating deep neural networksINTEL CORP·Filed 2021·Granted Jul 22, 2025·0 cites·25 claims
- 0962US12229673B2Sparsity-aware datastore for inference processing in deep neural network architecturesINTEL CORP·Filed 2021·Granted Feb 18, 2025·0 cites·25 claims
- 1062US7697364B2Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlinesBROADCOM CORP·Filed 2005·Granted Apr 13, 2010·4 cites·15 claims
- 1162US6806737B2Bi-directional amplifier and method for accelerated bus line communicationFiled 2003·Granted Oct 19, 2004·12 cites·25 claims
- 1261US8009506B2Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlinesBROADCOM CORP·Filed 2010·Granted Aug 30, 2011·2 cites·17 claims
- 1355US2023059976A1Deep neural network (dnn) accelerator facilitating quantized inferenceINTEL CORP·Filed 2022·Application pending·0 cites
- 1454US2022188075A1Floating point multiply-accumulate unit for deep learningINTEL CORP·Filed 2022·Application pending·0 cites
- 1553US2023140173A1Deep neural network (dnn) accelerators with heterogeneous tilingRaha Arnab·Filed 2022·Application pending·0 cites
- 1653US2022188638A1Data reuse in deep learningINTEL CORP·Filed 2022·Application pending·0 cites
- 1753US2022261623A1System and method for channel-separable operations in deep neural networksINTEL CORP·Filed 2022·Application pending·0 cites
- 1852US2022075659A1Runtime configurable register files for artificial intelligence workloadsINTEL CORP·Filed 2021·Application pending·0 cites
- 1951US2023351181A1Approximating activation functions with taylor seriesCHEEMA UMER IFTIKHAR·Filed 2023·Application pending·0 cites
- 2051US2023229507A1Scheduling computations in deep neural network based on sparsityINTEL CORP·Filed 2023·Application pending·0 cites
- 2150US7123056B2Clock logic domino circuits for high-speed and energy efficient microprocessor pipelinesMOSAID TECHNOLOGIES INC·Filed 2003·Granted Oct 17, 2006·5 cites·7 claims
- 2250US2023221994A1Dynamic uncompression for channel-separable operation in neural networkRaha Arnab·Filed 2023·Application pending·0 cites
- 2348US2023073661A1Accelerating data load and computation in frontend convolutional layerINTEL CORP·Filed 2022·Application pending·0 cites
- 2447US8477556B2Memory architecture having multiple partial wordline drivers and contacted and feed-through bitlinesSUNG RAYMOND J·Filed 2011·Granted Jul 2, 2013·1 cites·16 claims
- 2547US2023018857A1Sparsity processing on unpacked dataPOWER MARTIN·Filed 2022·Application pending·0 cites
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