Inventor · disambiguated record
Shi-Yu Huang
Also filed as: HUANG SHI · HUANG SHI-YU
10 granted patents·7 pending applications·57 citations·filing 1999–2020
85Inventor score
Files withMENTOR GRAPHICS CORP3PROCTER & GAMBLE2SIEMENS IND SOFTWARE INC2UNIV NAT TSING HUA2UNIV TSINGHUA2
Top patents by PatentIndex Score
17 records- 0180US11361248B2Multi-stage machine learning-based chain diagnosisSIEMENS IND SOFTWARE INC·Filed 2019·Granted Jun 14, 2022·5 cites·20 claims
- 0271US11681843B2Input data compression for machine learning-based chain diagnosisSIEMENS IND SOFTWARE INC·Filed 2019·Granted Jun 20, 2023·1 cites·21 claims
- 0371US10317462B2Wide-range clock signal generation for speed grading of logic coresMENTOR GRAPHICS CORP·Filed 2017·Granted Jun 11, 2019·1 cites·14 claims
- 0471US6351837B1High speed built-in self-test circuit for DRAMSTAIWAN SEMICONDUCTOR MFG CORP·Filed 1999·Granted Feb 26, 2002·32 cites·7 claims
- 0564US7370299B2Method and computer program product for register transfer level power estimation in chip designUNIV TSINGHUA·Filed 2005·Granted May 6, 2008·8 cites·12 claims
- 0657US11287471B1Electronic circuit for online monitoring a clock signalUNIV NAT TSING HUA·Filed 2020·Granted Mar 29, 2022·0 cites·10 claims
- 0753US2016055296A1Method And System For Assessing A Health ConditionPROCTER & GAMBLE·Filed 2014·Application pending·0 cites
- 0853US2014335534A1Method And System For Identifying A Biomarker Indicative Of Health ConditionPROCTER & GAMBLE·Filed 2014·Application pending·0 cites
- 0952US9720038B2Method and circuit of pulse-vanishing testMENTOR GRAPHICS CORP·Filed 2014·Granted Aug 1, 2017·0 cites·10 claims
- 1045US11190192B1Electronic device with fault and soft error tolerant delay-locked loopsUNIV NAT TSING HUA·Filed 2020·Granted Nov 30, 2021·0 cites·17 claims
- 1145US6647524B1Built-in-self-test circuit for RAMBUS direct RDRAMWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Nov 11, 2003·10 cites·4 claims
- 1244US2014246705A1Programmable Leakage Test For Interconnects In Stacked DesignsMENTOR GRAPHICS CORP·Filed 2014·Application pending·0 cites
- 1336US2008148119A1Apparatus for Built-in Speed Grading and Method for Generating Desired Frequency for the SameUNIV TSINGHUA·Filed 2006·Application pending·0 cites
- 1435US2016320445A1Probeless parallel test system and method for integrated circuitNAT UNIV TSING HUA·Filed 2015·Application pending·0 cites
- 1534US10402523B2System for monitoring electronic circuit and method for monitoring electronic circuitIND TECH RES INST·Filed 2015·Granted Sep 3, 2019·0 cites·29 claims
- 1631US2013088268A1Multi-Phase Clock Generation System and Clock Calibration Method ThereofDING RUO-TING·Filed 2012·Application pending·0 cites
- 1724US2012133444A1Phase-locked loop device and clock calibration method thereofTZENG CHAO-WEN·Filed 2011·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →