Inventor · disambiguated record
Bulent Dervisoglu
Also filed as: DERVISOGLU BULENT · DERVISOGLU BULENT I
18 granted patents·1 pending application·825 citations·filing 1990–2015
96Inventor score
Files withON CHIP TECHNOLOGIES INC7CADENCE DESIGN SYSTEMS INC3DERVISOGLU BULENT2DERVISOGLU BULENT I2HEWLETT PACKARD CO2
Top patents by PatentIndex Score
19 records- 0197US6631504B2Hierarchical test circuit structure for chips with multiple circuit blocksCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Oct 7, 2003·122 cites·17 claims
- 0297US6594802B1Method and apparatus for providing optimized access to circuits for debug, programming, and testINTELLITECH CORP·Filed 2000·Granted Jul 15, 2003·143 cites·40 claims
- 0397US5257223AFlip-flop circuit with controllable copying between slave and scan latchesHEWLETT PACKARD CO·Filed 1991·Granted Oct 26, 1993·138 cites·19 claims
- 0496US6687865B1On-chip service processor for test and debug of integrated circuitsON CHIP TECHNOLOGIES INC·Filed 1999·Granted Feb 3, 2004·110 cites·22 claims
- 0595US7890899B2Variable clocked scan test improvementsINTELLECTUAL VENTURES I LLC·Filed 2008·Granted Feb 15, 2011·27 cites·14 claims
- 0694US7353470B2Variable clocked scan test improvementsON CHIP TECHNOLOGIES INC·Filed 2005·Granted Apr 1, 2008·27 cites·18 claims
- 0793US6886121B2Hierarchical test circuit structure for chips with multiple circuit blocksCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Apr 26, 2005·60 cites·8 claims
- 0888US7197681B2Accelerated scan circuitry and method for reducing scan test data volume and execution timeON CHIP TECHNOLOGIES INC·Filed 2004·Granted Mar 27, 2007·39 cites·12 claims
- 0988US7188286B2Accelerated scan circuitry and method for reducing scan test data volume and execution timeON CHIP TECHNOLOGIES INC·Filed 2004·Granted Mar 6, 2007·32 cites·6 claims
- 1085US7200784B2Accelerated scan circuitry and method for reducing scan test data volume and execution timeON CHIP TECHNOLOGIES INC·Filed 2004·Granted Apr 3, 2007·26 cites·7 claims
- 1185US7181705B2Hierarchical test circuit structure for chips with multiple circuit blocksCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Feb 20, 2007·32 cites·37 claims
- 1285US7080301B2On-chip service processorON CHIP TECHNOLOGIES INC·Filed 2005·Granted Jul 18, 2006·8 cites·6 claims
- 1384US8239716B2On-chip service processorDERVISOGLU BULENT I·Filed 2010·Granted Aug 7, 2012·4 cites·3 claims
- 1483US7752515B2Accelerated scan circuitry and method for reducing scan test data volume and execution timeDERVISOGLU BULENT I·Filed 2007·Granted Jul 6, 2010·10 cites·7 claims
- 1578US7836371B2On-chip service processorDERVISOGLU BULENT·Filed 2006·Granted Nov 16, 2010·6 cites·10 claims
- 1677US6964001B2On-chip service processorON CHIP TECHNOLOGIES INC·Filed 2004·Granted Nov 8, 2005·12 cites·6 claims
- 1774US5068881AScannable register with delay test capabilityHEWLETT PACKARD CO·Filed 1990·Granted Nov 26, 1991·28 cites·26 claims
- 1869US8996938B2On-chip service processorDERVISOGLU BULENT·Filed 2011·Granted Mar 31, 2015·1 cites·22 claims
- 1953US2016011260A1On-Chip Service ProcessorINTELLECTUAL VENTURES LLC·Filed 2015·Application pending·0 cites
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