Inventor · disambiguated record
Andrey Nikitin
Also filed as: NIKITIN ANDREY · NIKITIN ANDREY A · NIKITIN ANDREY ANATOLEVICH
40 granted patents·207 citations·filing 2001–2012
97Inventor score
Files withLSI LOGIC CORP18LSI CORP14ANDREEV ALEXANDRE2NIKITIN ANDREY2ALEKSEEV DMITRIY VLADIMIROVICH1
Top patents by PatentIndex Score
40 records- 0191US8677306B1Microcontroller controlled or direct mode controlled network-fabric on a structured ASICEASIC CORP·Filed 2012·Granted Mar 18, 2014·59 cites·19 claims
- 0282US8516425B2Method and computer program for generating grounded shielding wires for signal wiringNIKITIN ANDREY·Filed 2012·Granted Aug 20, 2013·7 cites·25 claims
- 0381US8452006B2Cryptographic processing using a processorALEKSEEV DMITRIY VLADIMIROVICH·Filed 2010·Granted May 28, 2013·9 cites·23 claims
- 0479US7389484B2Method and apparatus for tiling memories in integrated circuit layoutLSI CORP·Filed 2005·Granted Jun 17, 2008·10 cites·20 claims
- 0575US7996804B2Signal delay skew reduction systemLSI CORP·Filed 2008·Granted Aug 9, 2011·6 cites·15 claims
- 0675US7039855B2Decision function generator for a Viterbi decoderLSI LOGIC CORP·Filed 2003·Granted May 2, 2006·20 cites·18 claims
- 0771US6651239B1Direct transformation of engineering change orders to synthesized IC chip designsLSI LOGIC CORP·Filed 2001·Granted Nov 18, 2003·16 cites·21 claims
- 0870US7168052B2Yield driven memory placement systemLSI LOGIC CORP·Filed 2004·Granted Jan 23, 2007·2 cites·16 claims
- 0969US7424687B2Method and apparatus for mapping design memories to integrated circuit layoutLSI CORP·Filed 2005·Granted Sep 9, 2008·6 cites·19 claims
- 1069US7380223B2Method and system for converting netlist of integrated circuit between librariesLSI CORP·Filed 2005·Granted May 27, 2008·4 cites·20 claims
- 1168US7584442B2Method and apparatus for generating memory models and timing databaseLSI CORP·Filed 2005·Granted Sep 1, 2009·3 cites·9 claims
- 1265US6615401B1Blocked net buffer insertionLSI LOGIC CORP·Filed 2002·Granted Sep 2, 2003·12 cites·12 claims
- 1364US8245168B2Method and apparatus for generating memory models and timing databaseANDREEV ALEXANDRE·Filed 2009·Granted Aug 14, 2012·2 cites·11 claims
- 1463US7200826B2RRAM memory timing learning toolLSI LOGIC CORP·Filed 2004·Granted Apr 3, 2007·9 cites·4 claims
- 1562US7512918B2Multimode delay analysis for simplifying integrated circuit design timing modelsLSI CORP·Filed 2005·Granted Mar 31, 2009·2 cites·3 claims
- 1661US8239813B2Method and apparatus for balancing signal delay skewNIKITIN ANDREY·Filed 2011·Granted Aug 7, 2012·1 cites·17 claims
- 1760US7257807B2Method for optimizing execution time of parallel processor programsLSI CORP·Filed 2003·Granted Aug 14, 2007·7 cites·9 claims
- 1858US8761916B2High-performance tone detection using a digital signal processor (DSP) having multiple arithmetic logic units (ALUs)LETUNOVSKIY ALEKSEY ALEXANDROVICH·Filed 2009·Granted Jun 24, 2014·3 cites·22 claims
- 1958US8037432B2Method and apparatus for mapping design memories to integrated circuit layoutLSI CORP·Filed 2008·Granted Oct 11, 2011·3 cites·12 claims
- 2058US7036102B2Process and apparatus for placement of cells in an IC during floorplan creationLSI LOGIC CORP·Filed 2003·Granted Apr 25, 2006·5 cites·17 claims
- 2156US7111264B2Process and apparatus for fast assignment of objects to a rectangleLSI LOGIC CORP·Filed 2003·Granted Sep 19, 2006·4 cites·20 claims
- 2255US8006209B2Method and system for outputting a sequence of commands and data described by a flowchartLSI CORP·Filed 2008·Granted Aug 23, 2011·0 cites·5 claims
- 2354US7415691B2Method and system for outputting a sequence of commands and data described by a flowchartLSI CORP·Filed 2004·Granted Aug 19, 2008·3 cites·20 claims
- 2454US7210113B2Process and apparatus for placing cells in an IC floorplanLSI LOGIC CORP·Filed 2004·Granted Apr 24, 2007·3 cites·18 claims
- 2553US7219321B2Process and apparatus for memory mappingLSI LOGIC CORP·Filed 2004·Granted May 15, 2007·2 cites·20 claims
- 2652US8566769B2Method and apparatus for generating memory models and timing databaseANDREEV ALEXANDRE·Filed 2012·Granted Oct 22, 2013·0 cites·13 claims
- 2752US7822099B2Digital Gaussian noise simulatorLSI CORP·Filed 2007·Granted Oct 26, 2010·0 cites·13 claims
- 2852US7315993B2Verification of RRAM tiling netlistLSI LOGIC CORP·Filed 2004·Granted Jan 1, 2008·2 cites·20 claims
- 2952US6901573B2Method for evaluating logic functions by logic circuits having optimized number of and/or switchesLSI LOGIC CORP·Filed 2003·Granted May 31, 2005·2 cites·23 claims
- 3050US8515055B2Adaptive filtering with flexible selection of algorithm complexity and performanceMAZURENKO IVAN LEONIDOVICH·Filed 2008·Granted Aug 20, 2013·0 cites·12 claims
- 3150US7193905B1RRAM flipflop rcell memory generatorLSI LOGIC CORP·Filed 2005·Granted Mar 20, 2007·3 cites·2 claims
- 3250US7155688B2Memory generation and placementLSI LOGIC CORP·Filed 2004·Granted Dec 26, 2006·1 cites·5 claims
- 3350US6701503B2Overlap remover managerLSI LOGIC CORP·Filed 2002·Granted Mar 2, 2004·1 cites·35 claims
- 3449US7328423B2Method for evaluating logic functions by logic circuits having optimized number of and/or switchesLSI LOGIC CORP·Filed 2005·Granted Feb 5, 2008·0 cites·8 claims
- 3548US7472358B2Method and system for outputting a sequence of commands and data described by a flowchartLSI CORP·Filed 2005·Granted Dec 30, 2008·0 cites·10 claims
- 3646US7404166B2Method and system for mapping netlist of integrated circuit to designLSI CORP·Filed 2005·Granted Jul 22, 2008·0 cites·17 claims
- 3746US7263470B2Digital gaussian noise simulatorLSI CORP·Filed 2003·Granted Aug 28, 2007·0 cites·12 claims
- 3845US7082593B2Method and apparatus of IC implementation based on C++ language descriptionLSI LOGIC CORP·Filed 2003·Granted Jul 25, 2006·0 cites·18 claims
- 3944US7103868B2Optimizing depths of circuits for Boolean functionsLSI LOGIC CORP·Filed 2002·Granted Sep 5, 2006·0 cites·23 claims
- 4038US7356743B2RRAM controller built in self test memoryLSI LOGIC CORP·Filed 2005·Granted Apr 8, 2008·0 cites·6 claims
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