Inventor · disambiguated record
Ramprasad Satagopan
Also filed as: SATAGOPAN RAMPRASAD
14 granted patents·1 pending application·804 citations·filing 1993–2004
95Inventor score
Top patents by PatentIndex Score
15 records- 0198US6310814B1Rambus DRAM (RDRAM) apparatus and method for performing refresh operationsRAMBUS INC·Filed 2000·Granted Oct 30, 2001·195 cites·40 claims
- 0296US7003639B2Memory controller with power management logicRAMBUS INC·Filed 2004·Granted Feb 21, 2006·126 cites·21 claims
- 0393US6021076AApparatus and method for thermal regulation in memory subsystemsRAMBUS INC·Filed 1998·Granted Feb 1, 2000·92 cites·20 claims
- 0489US6373768B2Apparatus and method for thermal regulation in memory subsystemsRAMBUS INC·Filed 1999·Granted Apr 16, 2002·110 cites·30 claims
- 0584US6640292B1System and method for controlling retire buffer operation in a memory systemRAMBUS INC·Filed 1999·Granted Oct 28, 2003·109 cites·17 claims
- 0677US6523089B2Memory controller with power management logicRAMBUS INC·Filed 2001·Granted Feb 18, 2003·19 cites·21 claims
- 0768US5513346AError condition detector for handling interrupt in integrated circuits having multiple processorsINTEL CORP·Filed 1993·Granted Apr 30, 1996·52 cites·18 claims
- 0863US6754783B2Memory controller with power management logicRAMBUS INC·Filed 2003·Granted Jun 22, 2004·7 cites·18 claims
- 0963US6571325B1Pipelined memory controller and method of controlling access to memory devices in a memory systemRAMBUS INC·Filed 1999·Granted May 27, 2003·36 cites·22 claims
- 1057US6782460B2Pipelined memory controller and method of controlling access to memory devices in a memory systemRAMBUS INC·Filed 2003·Granted Aug 24, 2004·4 cites·24 claims
- 1150US6195733B1Method to share memory in a single chip multiprocessor systemINTEL CORP·Filed 1998·Granted Feb 27, 2001·23 cites·6 claims
- 1248US5890013APaged memory architecture for a single chip multi-processor with physical memory pages that are swapped without latencyINTEL CORP·Filed 1996·Granted Mar 30, 1999·21 cites·6 claims
- 1345US2004139293A1System and method for controlling retire buffer operation in a memory systemRAMBUS INC·Filed 2003·Application pending·0 cites
- 1443US6453401B1Memory controller with timing constraint tracking and checking unit and corresponding methodRAMBUS INC·Filed 1999·Granted Sep 17, 2002·9 cites·26 claims
- 1528US5909702AMemory address translations for programs code execution/relocationINTEL CORP·Filed 1996·Granted Jun 1, 1999·1 cites·8 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →