Inventor · disambiguated record
Bruno Fel
Also filed as: FEL BRUNO
10 granted patents·129 citations·filing 1994–2018
89Inventor score
Files withST MICROELECTRONICS SA5SGS THOMSON MICROELECTRONICS2ST MICROELECTRONICS GRENOBLE 22THOMSON CSF SEMICONDUCTEURS1
Top patents by PatentIndex Score
10 records- 0188US10598728B2Scan chain circuit supporting logic self test pattern injection during run timeST MICROELECTRONICS GRENOBLE 2·Filed 2018·Granted Mar 24, 2020·3 cites·15 claims
- 0280US7281119B1Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modesST MICROELECTRONICS SA·Filed 2000·Granted Oct 9, 2007·35 cites·20 claims
- 0377US10613993B2Method for protecting a program code, corresponding system and processorST MICROELECTRONICS SA·Filed 2015·Granted Apr 7, 2020·3 cites·37 claims
- 0475US6732276B1Guarded computer instruction executionST MICROELECTRONICS SA·Filed 2000·Granted May 4, 2004·23 cites·14 claims
- 0573US6807626B1Execution of a computer programST MICROELECTRONICS SA·Filed 2000·Granted Oct 19, 2004·20 cites·13 claims
- 0671US9897653B2Scan chain circuit supporting logic self test pattern injection during run timeST MICROELECTRONICS GRENOBLE 2·Filed 2016·Granted Feb 20, 2018·1 cites·37 claims
- 0763US7111152B1Computer system that operates in VLIW and superscalar modes and has selectable dependency controlST MICROELECTRONICS SA·Filed 2000·Granted Sep 19, 2006·11 cites·13 claims
- 0848US6453385B1Cache systemSGS THOMSON MICROELECTRONICS·Filed 1998·Granted Sep 17, 2002·17 cites·20 claims
- 0943US5410506AMemory integrated circuit with protection against disturbancesTHOMSON CSF SEMICONDUCTEURS·Filed 1994·Granted Apr 25, 1995·9 cites·7 claims
- 1034US6546467B2Cache coherency mechanism using an operation to be executed on the contents of a location in a cache specifying an address in main memorySGS THOMSON MICROELECTRONICS·Filed 1998·Granted Apr 8, 2003·7 cites·20 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →