Inventor · disambiguated record
William C. Rash
Also filed as: RASH WILLIAM · RASH WILLIAM C
15 granted patents·3 pending applications·406 citations·filing 1999–2023
92Inventor score
Top patents by PatentIndex Score
18 records- 0195US6615366B1Microprocessor with dual execution core operable in high reliability modeINTEL CORP·Filed 1999·Granted Sep 2, 2003·292 cites·24 claims
- 0284US11403097B2Systems and methods to skip inconsequential matrix operationsINTEL CORP·Filed 2019·Granted Aug 2, 2022·3 cites·25 claims
- 0382US10235175B2Processors, methods, and systems to relax synchronization of accesses to shared memoryINTEL CORP·Filed 2016·Granted Mar 19, 2019·3 cites·18 claims
- 0480US11748130B2Virtualization and multi-tenancy support in graphics processorsINTEL CORP·Filed 2019·Granted Sep 5, 2023·2 cites·17 claims
- 0580US7340643B2Replay mechanism for correcting soft errorsINTEL CORP·Filed 2003·Granted Mar 4, 2008·26 cites·5 claims
- 0677US6625756B1Replay mechanism for soft error recoveryINTEL CORP·Filed 1999·Granted Sep 23, 2003·67 cites·16 claims
- 0776US12229581B2Virtualization and multi-tenancy support in graphics processorsINTEL CORP·Filed 2023·Granted Feb 18, 2025·0 cites·20 claims
- 0876US9703562B2Instruction emulation processors, methods, and systemsINTEL CORP·Filed 2013·Granted Jul 11, 2017·4 cites·15 claims
- 0975US9304940B2Processors, methods, and systems to relax synchronization of accesses to shared memoryINTEL CORP·Filed 2013·Granted Apr 5, 2016·3 cites·16 claims
- 1070US9354681B2Protected power management mode in a processorINTEL CORP·Filed 2013·Granted May 31, 2016·2 cites·19 claims
- 1169US10073513B2Protected power management mode in a processorINTEL CORP·Filed 2016·Granted Sep 11, 2018·1 cites·20 claims
- 1268US11900114B2Systems and methods to skip inconsequential matrix operationsINTEL CORP·Filed 2022·Granted Feb 13, 2024·0 cites·25 claims
- 1368US9323535B2Instruction order enforcement pairs of instructions, processors, methods, and systemsINTEL CORP·Filed 2013·Granted Apr 26, 2016·2 cites·24 claims
- 1461US9202056B2Inter-processor attestation hardwareINTEL CORP·Filed 2013·Granted Dec 1, 2015·1 cites·8 claims
- 1549US9395990B2Mode dependent partial width load to wider register processors, methods, and systemsINTEL CORP·Filed 2013·Granted Jul 19, 2016·0 cites·25 claims
- 1647US2021089316A1Deep learning implementations using systolic arrays and fused operationsINTEL CORP·Filed 2019·Application pending·0 cites
- 1744US2014281236A1Systems and methods for implementing transactional memoryRASH WILLIAM C·Filed 2013·Application pending·0 cites
- 1843US2014281398A1Instruction emulation processors, methods, and systemsRASH WILLIAM C·Filed 2013·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →