Inventor · disambiguated record
Yasutaka Tsukamoto
Also filed as: TSUKAMOTO YASUTAKA
12 granted patents·98 citations·filing 1997–2016
89Inventor score
Top patents by PatentIndex Score
12 records- 0181US7401277B2Semiconductor integrated circuit and scan test method thereforRICOH KK·Filed 2004·Granted Jul 15, 2008·26 cites·24 claims
- 0274US7310795B2Method and apparatus for simulating logic circuits that include a circuit block to which power is not suppliedRICOH KK·Filed 2005·Granted Dec 18, 2007·6 cites·7 claims
- 0372US6910202B2Logic synthesis device and logic synthesis methodRICOH KK·Filed 2002·Granted Jun 21, 2005·20 cites·8 claims
- 0460USRE43623EMethod and apparatus for simulating logic circuits that include a circuit block to which power is not suppliedTSUKAMOTO YASUTAKA·Filed 2009·Granted Aug 28, 2012·2 cites·21 claims
- 0553US8239834B2Method and system of program development supportingTSUKAMOTO YASUTAKA·Filed 2006·Granted Aug 7, 2012·1 cites·7 claims
- 0648US7971167B2Semiconductor design support device, semiconductor design support method, and manufacturing method for semiconductor integrated circuitRICOH CO LTD·Filed 2008·Granted Jun 28, 2011·0 cites·4 claims
- 0742US7343276B1Recording media including code for estimating IC power consumptionRICOH KK·Filed 1999·Granted Mar 11, 2008·14 cites·40 claims
- 0842US6094527AMethod and apparatus for estimating IC power consumptionRICOH KK·Filed 1997·Granted Jul 25, 2000·14 cites·6 claims
- 0939US8701061B2Semiconductor design support apparatusTSUKAMOTO YASUTAKA·Filed 2011·Granted Apr 15, 2014·0 cites·8 claims
- 1035US6093212AMethod for selecting operation cycles of a semiconductor IC for performing an IDDQ test by using a simulationRICOH KK·Filed 1998·Granted Jul 25, 2000·6 cites·23 claims
- 1135US6042613ALSI design aiding apparatusRICOH KK·Filed 1997·Granted Mar 28, 2000·9 cites·5 claims
- 1233US10339615B2Automatic IP core generation systemADAPT IP INC·Filed 2016·Granted Jul 2, 2019·0 cites·11 claims
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